US3582674A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic circuit
Assignee: American Microsystems Holding Corp
•
Filing: 1967-08-23
•
Granted: 1971-06-01
•
Expires: 1987-08-23
Abstract
Abstract A logic circuit is disclosed comprised of two separate but connectable sections, namely a complex gate section and a delay section. The gate section has five input terminals for receiving data and/or control input signals and a single output, the delay section having a single input and two outputs providing a 1-bit delay output and a complemented 1-bit delay. By means of various interconnections the circuit can provide a wide range of functional devices including various flip-flop arrangements with clear and load capabilities.
Inventors
- 👤 Alan E Pound
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:31
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018557; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/173; H03K19/1733; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K5/00; H03K5/13; H03K5/135
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
123 words
A logic circuit comprising a complex gate section and a connectable time delay section, said gate section including a first NOR gate circuit with a plurality of input connections and an output connection, an AND gate circuit with a plurality of input connections and an output connection, an independent data conductor, an OR gate circuit with a plurality of input connections and an output connection, means for interconnecting the output connection of said NOR gate circuit, and said AND gate circuit and said independent data conductor with the input connections of said OR gate circuit, and a time delay circuit having an input connection located adjacent and connectable to said output connection of said OR gate circuit and a pair of output connections.
Claim 2
Dependent Claim
123 words
A logic circuit comprising a complex gate section and a connectable time delay section, said gate section including a first NOR gate circuit with a plurality of input connections and an output connection, an AND gate circuit with a plurality of input connections and an output connection, an independent data conductor, an OR gate circuit with a plurality of input connections and an output connection, means for interconnecting the output connection of said NOR gate circuit, and said AND gate circuit and said independent data conductor with the input connections of said OR gate circuit, and a time delay circuit having an input connection located adjacent and connectable to said output connection of said OR gate circuit and a pair of output connections.
Claim 3
Dependent Claim
54 words
A logic circuit as claimed in claim 1 wherein said OR gate circuit comprises a second NOR gate circuit for receiving the output connections from said first NOR gate circuit, said AND gate circuit and said independent data conductor and An inverter circuit for receiving the output connection from said second NOR gate circuit.
Claim 4
Dependent Claim
53 words
A logic circuit as claimed in claim 1 wherein said delay section comprises means providing a true 1-bit delay output signal on a first output connection and a complemented 1-bit delay output signal on a second output connection of said delay section, and means for electrically isolating said first and second output connections.
Claim 5
Dependent Claim
27 words
A logic circuit as claimed in claim 1 comprising a direct connection extending between the output of said gate section and the input of said delay section.
Claim 6
Dependent Claim
27 words
A logic circuit as claimed in claim 3 comprising a direct connection extending between the output of said gate section and the input of said delay section.
Claim 7
Dependent Claim
57 words
A logic circuit as claimed in claim 5 and comprising a feedback connection connected to one output of said delay section and one of the input connections of said first NOR gate circuit and means for connecting one of the input connections of said AND gate circuit with the other input connection of said AND gate circuit.
Claim 8
Dependent Claim
45 words
A logic circuit as claimed in claim 5 and comprising a feedback connection connected to one output connection of said delay section and one of the input connections of said first NOR gate circuit and one of the input connections of said AND gate circuit.
Claim 9
Dependent Claim
35 words
A logic circuit as claimed in claim 4 and comprising means for interconnecting one of the input connections of said first NOR gate circuit with one of the input connections of said AND gate circuit.
Claim 10
Dependent Claim
35 words
A logic circuit as claimed in claim 8 and comprising means for interconnecting another of the input connections of said first NOR gate circuit with another of the input connections of said AND gate circuit.
Claim 11
Dependent Claim
52 words
A logic circuit as claimed in claim 5 and comprising a feedback connection connected to one output of said delay section and one of the inputs of said first NOR gate circuit and means interconnecting another input connection of said NOR gate circuit with one input connection of said AND gate circuit.
Claim 12
Dependent Claim
33 words
A logic circuit as claimed in claim 4 and comprising a feedback connection connected to one output of said delay section and one of the input connections of said first NOR gate circuit.
Claim 13
Dependent Claim
30 words
A logic circuit as claimed in claim 7 and comprising means interconnecting another input connection of said first NOR gate circuit with another input connection of said AND gate circuit.
Claim 14
Dependent Claim
32 words
A logic circuit as claimed in claim 4 and comprising a feedback connection connected to one output of said delay circuit and one of the input connections of said AND gate circuit.
Claim 15
Dependent Claim
46 words
A logic circuit as claimed in claim 5 and comprising a feedback connection connected to one output of said delay section and one of the input connections of said AND gate circuit and means interconnecting the other AND gate input to a first NOR gate input.
Claim 16
Dependent Claim
55 words
A logic circuit as claimed in claim 5 comprising a feedback connection connected to one output of said delay section and one of the input connections of said AND gate circuit, and means for connecting one of the input connections of said NOR gate circuit with the other input connection of said NOR gate circuit.
Claim 17
Dependent Claim
36 words
A logic delay circuit as claimed in claim 1 wherein said NOR gate circuit, said AND gate circuit, said OR gate circuit and said time delay section are formed from metal oxide semiconductor field effect devices.
Claim 18
Dependent Claim
37 words
A logic delay circuit as claimed in claim 4 wherein said NOR gate circuit, said AND gate circuit, said OR gate circuit and said time delay section are formed from monolithic metal oxide semiconductor field effect devices.
Claim 19
Dependent Claim
19 words
A logic circuit as claimed in claim 8 comprising means connecting said independent conductor to a logic 0 signal.
Claim 20
Dependent Claim
19 words
A logic circuit as claimed in claim 9 comprising means connecting said independent conductor to a logic 0 signal.
Claim 21
Dependent Claim
24 words
A logic circuit as claimed in claim 19 includiNg means connecting the output of said gate section with the input of said delay section.
References Cited (Backward Citations)
US3171972A
Cited
US3398296A
Cited
US3351778A
Cited
US3284645A
Cited
US3395292A
Cited
US3444395A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |