Bootstrapped inverter memory cell

Claim 2

A data storage cell comprising, a storage capacitor, first, second and third field effect transistors, said first and said third field effect transistors connected in electrical series between a reference voltage level and the gate electrode of said second field effect transistor, said storage capacitor connected between the gate electrode of said second field effect transistor and the gate electrode of said third field effect transistor, a data line connected at a common point between said first and third field effect transistors, said second field effect transistor connected between a first clock signal and the gate electrode on said third field effect transistor.

Claim 3

The data storage cell recited in claim 1 wherein said first clock signal is a recurring read clock signal said first field effect transistor includes a gate electrode connected to a recurring write clock signal for actuating said first field effect transistor during said recurring write interval, said secoNd field effect transistor conducting said recurring read clock signal to the gate electrode of said third field effect transistor during said recurring read interval as a function of the data stored on said storage capacitor, said third field effect transistor having its second electrode connected to a voltage level for representing one logic state, said one logic state being provided as an output from said storage cell when a voltage level representing a second logic state is stored by said storage capacitor.

Claim 4

The data storage cell recited in claim 2 and further wherein said data line provides input and output data.

Claim 5

The data storage cell recited in claim 2 further including a plurality of common lines for input and output data, said data storage cell connected between adjacent lines with a first electrode of said first field effect transistor connected to one line for receiving input data, and a first electrode of said third field effect transistor connected to an adjacent line for providing output data.

Claim 6

The data storage cell recited in claim 2 further including refresh circuitry means receiving output data from said storage cell, said refresh circuitry including means for inverting said data and providing said inverted data as an input to said storage cell during the write interval of a data refresh operating cycle.

Claim 7

The refresh circuitry recited in claim 5 including a blocking field effect transistor for interrupting the flow of output data into said refresh circuitry means when said storage cell is being externally addressed for enabling new data to be stored by said storage cell.

Claim 8

The refresh circuitry recited in claim 6 further including two channels including a common output connection between said channels, said common connection being connected to common line, a first of said channels inverting logic data representing one logic state for providing an output on said common output terminal, a second channel inverting logic data of a second logic state for providing an output on said common output terminal.

Claim 9

The data storage cell recited in claim 1 wherein said data storage cell comprises one of a plurality of data storage cells connected to data line, said data line providing a common conductor for input and output data, a fourth field effect transistor connected to said common input/output data line for charging said line to a first voltage level representing one logic state during a precharge interval between said read and write intervals, said third field effect transistor connected to said common input/output data line for either connecting said data line to said reference voltage level or for isolating said data line from said reference voltage level during said read interval as a function of the logic state of the data stored by said cell.

Claim 10

The data storage cell recited in claim 1 wherein said data storage cell comprises one of a plurality of data storage cells connected between adjacent input/output data lines, means for providing data to be written into an addressed data storage cell from one input/output data line and means for receiving output data from an addressed data storage cell on an adjacent input/output data line.

Claim 11

The data storage cell recited in claim 1 further including means for providing a read signal to an addressed data cell during a read recurring interval including delay circuitry for delaying said read signal for one interval for converting said read signal to a write signal.

Claim 12

A data storage circuit comprising, a first field effect transistor having a first electrode for receiving data being stored and for receiving refreshed data previously stored, and having a second electrode, said first field effect transistor having its gate electrode connected to a write signal, a second field effect transistor having a first electrode connected to electrical ground representing one logic state and a second electrode connected to control output voltage levels representing first and second Logic states, said second field effect transistor providing an output voltage level representing the inverse logic state of the data stored by said data cell, a third field effect transistor having a first electrode connected to a read signal and having its gate electrode connected to the second electrode of said first field effect transistor and having a second electrode connected to the gate electrode of said second field effect transistor, a storage capacitor connected between the gate electrode and second electrode of said third field effect transistor for storing voltage levels representing the logic states of data being stored by said data storage circuit and for providing a feedback voltage from the second electrode of said third field effect transistor to the gate electrode of said third field effect transistor during said read interval for enhancing the conduction of said third field effect transistor when data of said second logic state is stored on said capacitor, the enhanced conduction of said third field effect transistor providing a relatively higher drive voltage on the gate electrode of said second field effect transistor for increasing the speed of operation of said data storage cell.

Claim 13

A data storage circuit comprising, a first field effect transistor having a first electrode for receiving data being stored and for receiving refreshed data previously stored, and having a second electrode, said first field effect transistor having its gate electrode connected to a write signal, a second field effect transistor having a first electrode connected to electrical ground representing one logic state and a second electrode connected to control output voltage levels representing first and second Logic states, said second field effect transistor providing an output voltage level representing the inverse logic state of the data stored by said data cell, a third field effect transistor having a first electrode connected to a read signal and having its gate electrode connected to the second electrode of said first field effect transistor and having a second electrode connected to the gate electrode of said second field effect transistor, a storage capacitor connected between the gate electrode and second electrode of said third field effect transistor for storing voltage levels representing the logic states of data being stored by said data storage circuit and for providing a feedback voltage from the second electrode of said third field effect transistor to the gate electrode of said third field effect transistor during said read interval for enhancing the conduction of said third field effect transistor when data of said second logic state is stored on said capacitor, the enhanced conduction of said third field effect transistor providing a relatively higher drive voltage on the gate electrode of said second field effect transistor for increasing the speed of operation of said data storage cell.

Claim 14

The data storage circuit recited in claim 11 including a common input/output line for said data, and a precharge field effect transistor for charging said input/output line to a voltage level representing a first logic state during an interval between said write and read operating intervals, said input/output line being discharged or remaining charged as a function of the state of said stored data during said read interval.

Claim 15

The data storage circuit recited in claim 12 including circuitry means for restoring the voltage level of the data stored by said storage capacitor following each read interval, and periodically when said storage cell is not frequently addressed.