US3581292A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Read/write memory circuit
Assignee: Boeing North American Inc
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Filing: 1969-01-07
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Granted: 1971-05-25
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Expires: 1989-01-07
Abstract
Abstract Two capacitors of an addressed memory circuit are charged during a write period to a potential representing a logical state. The first capacitor is connected between the output electrode and the control electrode of the MOS device for turning the MOS device on as a function of the logical state of the capacitor. When the input signal is true, during a read period, the voltage on the output electrode of the MOS device is fed back through the first capacitor for increasing the voltage. As a result, the output voltage is driven to a voltage which overcomes the threshold drop through the device. Another MOS device having a relatively larger control voltage is turned on so that the read signal appearing at the output electrode of the first MOS device is read out of the address memory circuit without a reduction due to threshold voltages of the MOS devices involved. The second capacitor connected between the common input/output line and ground is recharged so that it supplies leakage charge to the first capacitor during write periods when the circuit is not addressed. It is conditionally reset to ground between read and write periods to prevent reading of erroneous information.
Inventors
- 👤 Robert W Polkinghorn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
176 words
In combination: output means, first field effect transistor means having a first electrode, a second electrode, and a control electrode, said first electrode being connected to said output means during certain time intervals for providing output voltage levels equivalent to voltage levels on said first electrode, a storage capacitor connected between said first electrode and said control electrode for feeding back changes in voltage levels on said first electrode to said control electrode, second field effect transistor means for connecting voltage levels representing logic states to the control electrode of said first field effect transistor means and to the storage capacitor during one time interval, and for isolating said control electrode and storage capacitor from said voltage levels during subsequent time intervals, said storage capacitor storing a charge equivalent to said voltage levels, means connected to the second electrode of said first field effect transistor means for providing voltage levels to said first electrode during said one time interval and during a subsequent time interval as a function of the voltage levels of said storage capacitor.
Claim 2
Dependent Claim
176 words
In combination: output means, first field effect transistor means having a first electrode, a second electrode, and a control electrode, said first electrode being connected to said output means during certain time intervals for providing output voltage levels equivalent to voltage levels on said first electrode, a storage capacitor connected between said first electrode and said control electrode for feeding back changes in voltage levels on said first electrode to said control electrode, second field effect transistor means for connecting voltage levels representing logic states to the control electrode of said first field effect transistor means and to the storage capacitor during one time interval, and for isolating said control electrode and storage capacitor from said voltage levels during subsequent time intervals, said storage capacitor storing a charge equivalent to said voltage levels, means connected to the second electrode of said first field effect transistor means for providing voltage levels to said first electrode during said one time interval and during a subsequent time interval as a function of the voltage levels of said storage capacitor.
Claim 3
Dependent Claim
93 words
The combination recited in claim 1 including a third field effect transistor means connected in electrical parallel with said first field effect transistor means, said third field effect transistor means being conductive during said one time interval for coNnecting the first electrode of said first field effect transistor means to a voltage level, said storage capacitor storing charge representing the difference between the voltage level on said control electrode of said first field effect transistor and the voltage level on the first electrode of said first field effect transistor during said one interval.
Claim 4
Dependent Claim
126 words
A memory system having a storage circuit comprising: switching device means having an output electrode and a control electrode, capacitor means for storing a potential representing a logical state during a first interval, said capacitor means connected between said output electrode and said control electrode and said control electrode for feeding back voltage on the output electrode to said control electrode during a subsequent interval, said switching device means being responsive to said potential for driving said output electrode to a voltage representing a logical state as a function of the potential stored by said capacitor means during said first interval and as a function of the voltage fed back through said capacitor means to its control electrode from its output electrode during said subsequent interval.
Claim 5
Dependent Claim
126 words
A memory system having a storage circuit comprising: switching device means having an output electrode and a control electrode, capacitor means for storing a potential representing a logical state during a first interval, said capacitor means connected between said output electrode and said control electrode and said control electrode for feeding back voltage on the output electrode to said control electrode during a subsequent interval, said switching device means being responsive to said potential for driving said output electrode to a voltage representing a logical state as a function of the potential stored by said capacitor means during said first interval and as a function of the voltage fed back through said capacitor means to its control electrode from its output electrode during said subsequent interval.
Claim 6
Dependent Claim
78 words
The combination recited in claim 3 wherein: said first interval is a recurring write interval, said memory system further including write means for providing said potential to said capacitor means from an input during the write interval when said storage circuit is addressed and for restoring any leakage charge to said capacitor means during subsequent write intervals when said storage circuit is not addressed, said write means electrically isolating said capacitor means from the input during other intervals.
Claim 7
Dependent Claim
55 words
The combination recited in claim 3, including: an input/output conductor connected to said storage circuit, said switching device means comprising a first field effect transistor, a second field effect transistor connecting said input/output conductor to the output electrode of said first field effect transistor when said output electrode is at an electrical ground voltage level.
Claim 8
Dependent Claim
113 words
The combination recited in claim 5, wherein said first interval is a write interval of a memory read/write cycle and said storage circuit further includes a third field effect transistor conductive during said write interval for connecting said input/output conductor to said capacitor means for storing a potential representing a logic state, said third field effect transistor being nonconductive between write intervals of consecutive memory read/write cycles for isolating said capacitor means from potentials representing logic states when said circuit is not addressed by said memory system said third field effect transistor being conductive during each write interval even if said circuit is not addressed for supplying leakage charge to said capacitor means.
Claim 9
Dependent Claim
45 words
The combination recited in claim 5 wherein said second field effect transistor includes a control electrode connected to a signal which has a voltage level for overcoming the threshold voltage loss across said second field effect transistor when said second field effect transistor is conducting.
Claim 10
Dependent Claim
30 words
The combination recited in claim 3, including a plurality of said storage circuits connected in a memory system having an address matrix for addressing selected ones of said storage circuits.
Claim 11
Dependent Claim
66 words
The combination recited in claim 3 wherein said memory system includes an address matrix for addressing said storage circuit and a resetting field effect transistor connected between said matrix and electrical ground and having a control electrode, means connected to said control electrode for turning said resetting field effect transistor on during a memory cycle for discharging the inherent capacitance of said matrix to electrical ground.
Claim 12
Dependent Claim
103 words
A MOS storage circuit comprising MOS device means and having an output electrode and a control electrode capacitor means, means for initially charging said capacitor meaNs to a potential representing a logical state, said capacitor means being connected between the output electrode and the control electrode of said MOS device means for feeding back voltage on said output electrode for increasing the drive voltage on said control electrode, said MOS device means responsive to the charge on said capacitor means for driving its output electrode to a voltage level representing said logical state, said voltage level being in excess of said initial potential.
Claim 13
Dependent Claim
103 words
A MOS storage circuit comprising MOS device means and having an output electrode and a control electrode capacitor means, means for initially charging said capacitor meaNs to a potential representing a logical state, said capacitor means being connected between the output electrode and the control electrode of said MOS device means for feeding back voltage on said output electrode for increasing the drive voltage on said control electrode, said MOS device means responsive to the charge on said capacitor means for driving its output electrode to a voltage level representing said logical state, said voltage level being in excess of said initial potential.
Claim 14
Dependent Claim
38 words
The combination recited in claim 10 wherein said means for initially charging said capacitor means comprises a field effect transistor rendered nonconductive after said initial charging for electrically isolating said capacitor means until said capacitor means is recharged.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-24 | 1974-11-23 | 1975-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-24 | 1978-11-23 | 1979-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-24 | 1982-11-23 | 1983-05-25 | $7700.00 | Window Closed / Lapsed |