Patent US20030102518A1 successfully refreshed from Google Patents.
US20030102518A1
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US
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Finfet SRAM cell using low mobility plane for cell stability and method for forming
Assignee: GlobalFoundries US Inc
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Filing: 2001-12-04
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Granted: —
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Expires: 2021-12-04
Abstract
Abstract The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation
Inventors
- 👤 David Fried
- 👤 Randy Mann
- 👤 K. Muller
- 👤 Edward Nowak
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:34
CPC Classifications
H; H10; H10B; H10B10/00; H10D; H10D86/00; H10D86/01; H10D86/201; H10D30/00; H10D30/60; H10D30/62; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
87 words
1 . A method of forming a semiconductor device, the method comprising the steps of: forming a fin body, wherein the fin body has a first portion with a sidewall on a first plane that provides a first carrier mobility, and wherein the fin body has a second portion with a sidewall on a second plane that provides a second carrier mobility; forming a transfer transistor at the first portion of the fin body; and forming a latch transistor at the second portion of the fin body.
Claim 2
Dependent Claim
87 words
1 . A method of forming a semiconductor device, the method comprising the steps of: forming a fin body, wherein the fin body has a first portion with a sidewall on a first plane that provides a first carrier mobility, and wherein the fin body has a second portion with a sidewall on a second plane that provides a second carrier mobility; forming a transfer transistor at the first portion of the fin body; and forming a latch transistor at the second portion of the fin body.
Claim 3
Dependent Claim
24 words
2 . The method of claim 1 wherein the transfer transistor comprises an n-channel transistor and wherein the latch transistor comprises an n-channel transistor.
Claim 4
Dependent Claim
19 words
3 . The method of claim 1 wherein the first carrier mobility is less than the second carrier mobility.
Claim 5
Dependent Claim
47 words
4 . The method of claim 3 wherein the transfer transistor has a gain, and the latch transistor has a gain, and wherein the transfer transistor gain is less than the latch transistor gain due to the first carrier mobility being less than the second carrier mobility.
Claim 6
Dependent Claim
24 words
5 . The method of claim 1 wherein the first plane comprises a {110} plane and wherein the second plane comprises a {100} plane.
Claim 7
Dependent Claim
24 words
6 . The method of claim 1 wherein the step of forming the fin body comprises forming the fin body using sidewall image transfer.
Claim 8
Dependent Claim
37 words
7 . The method of claim 1 wherein the transfer transistor and the storage transistor are formed as part of a memory cell, and wherein the transfer transistor is coupled to pass data to the storage transistor.
Claim 9
Dependent Claim
16 words
8 . The method of claim 8 wherein the memory cell comprises an SRAM memory cell.
Claim 10
Dependent Claim
90 words
9 . The method of claim 1 further comprising the steps of: forming a second fin body, wherein the second fin body has a first portion with a sidewall on a first plane that provides a first carrier mobility, and wherein the second fin body has a second portion with a sidewall on a second plane to provides a second carrier mobility; forming a second transfer transistor at the first portion of the second fin body; and forming a second latch transistor at the second portion of the fin body.
Claim 11
Dependent Claim
75 words
10 . A semiconductor structure comprising: a fin body, wherein the fin body has a first portion with a sidewall on a first plane that provides a first carrier mobility, and wherein the fin body has a second portion with a sidewall on a second plane that provides a second carrier mobility; a transfer transistor at the first portion of the fin body; and a latch transistor at the second portion of the fin body.
Claim 12
Dependent Claim
75 words
10 . A semiconductor structure comprising: a fin body, wherein the fin body has a first portion with a sidewall on a first plane that provides a first carrier mobility, and wherein the fin body has a second portion with a sidewall on a second plane that provides a second carrier mobility; a transfer transistor at the first portion of the fin body; and a latch transistor at the second portion of the fin body.
Claim 13
Dependent Claim
25 words
11 . The semiconductor structure of claim 10 wherein the transfer transistor comprises an n-channel transistor and wherein the latch transistor comprises an n-channel transistor.
Claim 14
Dependent Claim
20 words
12 . The semiconductor structure of claim 10 wherein the first carrier mobility is less than the second carrier mobility.
Claim 15
Dependent Claim
48 words
13 . The semiconductor structure of claim 12 wherein the transfer transistor has a gain, and the latch transistor has a gain, and wherein the transfer transistor gain is less than the latch transistor gain due to the first carrier mobility being less than the second carrier mobility.
Claim 16
Dependent Claim
25 words
14 . The semiconductor structure of claim 10 wherein the first plane comprises a {110} plane and wherein the second plane comprises a {100} plane.
Claim 17
Dependent Claim
37 words
15 . The semiconductor structure of claim 10 wherein the transfer transistor and the storage transistor are a part of a memory cell, and wherein the transfer transistor is coupled to pass data to the storage transistor.
Claim 18
Dependent Claim
30 words
16 . The semiconductor structure of claim 12 wherein the transfer transistor comprises a portion a memory cell, and wherein the latch comprises a storage latch for the memory cell.
Claim 19
Dependent Claim
17 words
17 . The semiconductor structure of claim 16 wherein the memory cell comprises an SRAM memory cell.
Claim 20
Dependent Claim
106 words
18 . A memory cell comprising: a first transfer transistor, wherein the first transfer transistor includes a first fin body having a first sidewall; a second transfer transistor, wherein the second transfer transistor includes a second fin body having a second sidewall; and a storage latch coupled to the first and second transfer transistors to receive data from the first and second transfer transistors, wherein the storage latch comprises first and second storage latch transistors, and wherein the first storage latch transistor includes a third fin body having a third sidewall and wherein the second storage latch transistor has a fourth body having a fourth sidewall.
Claim 21
Dependent Claim
106 words
18 . A memory cell comprising: a first transfer transistor, wherein the first transfer transistor includes a first fin body having a first sidewall; a second transfer transistor, wherein the second transfer transistor includes a second fin body having a second sidewall; and a storage latch coupled to the first and second transfer transistors to receive data from the first and second transfer transistors, wherein the storage latch comprises first and second storage latch transistors, and wherein the first storage latch transistor includes a third fin body having a third sidewall and wherein the second storage latch transistor has a fourth body having a fourth sidewall.
Claim 22
Dependent Claim
92 words
19 . The memory cell of claim 18 wherein the first sidewall is oriented on a first crystal plane, and wherein the second sidewall is oriented on a second crystal plane, and wherein the third sidewall is oriented on a third crystal plane, and wherein the fourth sidewall is oriented on a fourth crystal plane, and wherein the first, second, third and fourth crystal planes are selected to provide a greater carrier mobility in the first and second storage latch transistors than the carrier mobility in the first and second transfer transistors.
Claim 23
Dependent Claim
46 words
20 . The memory cell of claim 19 wherein the first transfer transistor comprises a n-channel transistor and wherein the first plane comprises a {110} plane and wherein the first storage latch transistor comprises an n-channel transistor and wherein the third plane comprises a {100} plane.
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