Field effect transistor with higher mobility

Claim 2

In an integrated circuit with at least one field effect transistor (FET) having a source, drain and gate with the source and drain separated by a channel under the gate, comprising: a {100} monocrystalline silicon substrate having (100) and (110) crystal planes and 100! and 110! crystal directions; a FET gate having a length and a width and being insulated from the substrate by a silicon oxide layer thermally grown in the silicon substrate and aligned with the 100! crystal direction, said gate being patterned with the gate width in the 110! crystal direction so that the gate width is aligned approximately orthogonal to the (110) crystal plane and parallel with the 110! crystal direction; a source on one side of said patterned gate width and a drain on the other side of the patterned gate width, with impurities of the source and drain being disposed in the silicon substrate aligned with the 100! crystal direction; and a channel being formed under the gate between the source and drain when voltage is applied and being aligned in a direction parallel with the direction of the gate width, whereby the performance of the FET is enhanced due to a higher mobility of the carriers in the 110! crystal direction and due to the high quality of the silicon oxide layer insulating the gate from the substrate by being disposed in the 100! crystal direction.

Claim 3

The integrated circuit of claim 1 in which the mobility of the carriers in the 110! crystal direction is at least about 5% greater than the mobility of carriers in the 100! crystal direction.

Claim 4

The integrated circuit of claim 1 wherein at least one bipolar transistor is included in the circuit and the active regions of the bipolar transistor are aligned with 100! crystal direction of the silicon substrate.

Claim 5

The integrated circuit of claim 1 wherein field oxide, which is at end of the source and drain opposite from the gate of the FET, is in parallel alignment with the 100! crystal direction.

Claim 6

The integrated circuit of claim 1 wherein each of the opposite sides of the gate width is in contact with a sidewall of insulating material aligned parallel with the 100! crystal direction of silicon substrate.

Claim 7

The integrated circuit of claim 5 wherein impurities of a lightly doped drain, which is under each sidewall of insulating material, are in the silicon substrate and aligned with the 100! crystal direction of the silicon substrate.

Claim 8

An integrated circuit with a plurality of field effect transistors (FETs), each having a source, drain and gate with the source and drain separated by a channel under the gate, comprising: a (100) monocrystalline silicon substrate having (100) and (110) crystal planes and 100! and 110! crystal directions; a gate for each of a plurality of FETs with each of the gates having a length and a width and being insulated from the substrate by a thermally grown silicon oxide layer aligned with the 100! crystal direction of the silicon substrate, each of the gates being patterned with the gate width in the 110! crystal direction of the silicon substrate so that the gate width is aligned approximately orthogonal to (110) crystal plane and parallel with the 110! crystal direction; a source on one side of each of said patterned gate widths and a drain on the other side of each of the patterned gate widths, with impurities of the source and drain being disposed in the silicon substrate aligned with the 100! crystal direction; and a channel being formed under each of the gates between the source and drain of the respective gate when voltage is applied and each channel being aligned in a direction parallel with the direction of the gate width, whereby the performance of the FETs are enhanced due to a higher mobility of the carriers in the 110! crystal direction and due to the high quality of the silicon oxide layer insulating the gate from the silicon substrate by being disposed in the 100! crystal direction.

Claim 9

An integrated circuit with a plurality of field effect transistors (FETs), each having a source, drain and gate with the source and drain separated by a channel under the gate, comprising: a (100) monocrystalline silicon substrate having (100) and (110) crystal planes and 100! and 110! crystal directions; a gate for each of a plurality of FETs with each of the gates having a length and a width and being insulated from the substrate by a thermally grown silicon oxide layer aligned with the 100! crystal direction of the silicon substrate, each of the gates being patterned with the gate width in the 110! crystal direction of the silicon substrate so that the gate width is aligned approximately orthogonal to (110) crystal plane and parallel with the 110! crystal direction; a source on one side of each of said patterned gate widths and a drain on the other side of each of the patterned gate widths, with impurities of the source and drain being disposed in the silicon substrate aligned with the 100! crystal direction; and a channel being formed under each of the gates between the source and drain of the respective gate when voltage is applied and each channel being aligned in a direction parallel with the direction of the gate width, whereby the performance of the FETs are enhanced due to a higher mobility of the carriers in the 110! crystal direction and due to the high quality of the silicon oxide layer insulating the gate from the silicon substrate by being disposed in the 100! crystal direction.

Claim 10

The integrated circuit of claim 7 in which the mobility of the carriers in the 110! crystal direction is at least 5% greater than the mobility of carriers in the 100! crystal direction.

Claim 11

The integrated circuit of claim 7 wherein at least one bipolar transistor is included in the circuit and the active regions of the bipolar transistor are aligned with 100! crystal direction of the silicon substrate.

Claim 12

The integrated circuit of claim 7 wherein the FETs are separated from each other by field oxide in parallel alignment with the 100! crystal direction.

Claim 13

The integrated circuit of claim 7 wherein each of the opposite sides of each of the gate width is in contact with a sidewall of insulating material aligned with the 100! crystal direction of silicon substrate.

Claim 14

The integrated circuit of claim 11 wherein impurities of a lightly doped drain, which is under each sidewall of insulating material, are in the silicon substrate and aligned with the 100! crystal direction of the silicon substrate.