Method of making field effect transistor with higher mobility

Claim 3

The method of claim 1 wherein said exposing step is to deep ultra violet radiation and said wafer carries a resist material sensitive to said radiation.

Claim 4

The method of claim 1 wherein said images are contained in a series of masks in a rotatable holder and the holder is rotated 45° to align the channel to be formed approximately parallel with [110] crystal direction in the {100} wafer.

Claim 5

The method of claim 1 wherein said images are contained in a series of masks and the {100} wafer is positioned in a rotatable holder and the holder is rotated 45° to align the channel to be formed approximately parallel with [110] crystal direction in the {100} wafer.

Claim 6

The method of claim 1 wherein said images are created by exposure of a resist by an electron beam with the beam controlled to write the images on the {100} wafer so that the channel to be formed will be approximately parallel with [110] crystal direction in the {100} wafer.

Claim 7

The method of claim 1 wherein said images are contained in an x-ray mask and the exposure of a resist on the {100} wafer is by x-rays.

Claim 10

The method of claim 7 wherein, before the {100} wafer is positioned for exposure, a silicon oxide layer is thermally grown in the silicon substrate and aligned with the [100] crystal direction.

Claim 11

The method of claim 7 wherein, after the {100} wafer is positioned in the [100] crystal direction, the source and the drain are formed while the wafer is in the [100] crystal direction.

Claim 12

The method of claim 7 wherein, after the gate pattern is created, the {100} wafer is rotated 45° for at least one of the following fabrication steps.

Claim 13

The method of claim 10 wherein lightly doped drains are formed in the {100} silicon wafer with the gate serving as an alignment mask as one of the following fabrication steps.

Claim 14

The method of claim 11 wherein sidewall spacers are formed on the gate as one of the following fabrication steps.

Claim 15

In a method of fabricating an integrated circuit with at least one field effect transistor (FET) comprising the steps of: positioning a {100} monocrystalline silicon substrate having (100) and (110) crystal planes and [100] and [110] crystal directions for exposing the wafer to images for fabricating at least one FET; thermally growing a silicon oxide layer in the silicon substrate and aligned with the [100] crystal direction; creating a gate pattern having a gate width in the [110] crystal direction so that the gate width is aligned approximately orthogonal to the (110) crystal plane and parallel with the [110] crystal direction; forming a source on one side of gate width and a drain on the other side of the gate width; and creating a channel under the gate between the source and drain aligned in a direction parallel with the [110] crystal direction of the gate width, whereby the performance of the FET is enhanced due to a higher mobility of the carriers in the [110] crystal direction and due to the high quality of the silicon oxide layer insulating the gate from the substrate by being disposed in the [100] crystal direction.

Claim 16

In a method of fabricating an integrated circuit with at least one field effect transistor (FET) comprising the steps of: positioning a {100} monocrystalline silicon substrate having (100) and (110) crystal planes and [100] and [110] crystal directions for exposing the wafer to images for fabricating at least one FET; thermally growing a silicon oxide layer in the silicon substrate and aligned with the [100] crystal direction; creating a gate pattern having a gate width in the [110] crystal direction so that the gate width is aligned approximately orthogonal to the (110) crystal plane and parallel with the [110] crystal direction; forming a source on one side of gate width and a drain on the other side of the gate width; and creating a channel under the gate between the source and drain aligned in a direction parallel with the [110] crystal direction of the gate width, whereby the performance of the FET is enhanced due to a higher mobility of the carriers in the [110] crystal direction and due to the high quality of the silicon oxide layer insulating the gate from the substrate by being disposed in the [100] crystal direction.

Claim 17

The method of claim 13 wherein the integrated circuit is fabricated with a plurality of field effect transistors.

Claim 18

The method of claim 13 wherein the gate pattern is created by exposing a layer of gate material to an image pattern and removing part of the gate material.

Claim 19

The method of claim 15 wherein, before creating the gate pattern, the {100} wafer is rotated 45° to position the wafer in the [110] crystal direction.

Claim 20

The method of claim 15 wherein, after creating the gate pattern, the {100} wafer is rotated 45° to position the wafer in the [100] crystal direction for at least one of the remaining fabrication steps.

Claim 21

The method of claim 17 wherein the source and the drain are formed while the {100} wafer is in the [100] crystal direction.

Claim 22

The method of claim 13 wherein, after the {100} wafer fabrication is complete, the wafer is diced into individual chips and the chip edges are along the [110] direction.

Claim 23

The method of claim 19 wherein the {100} wafer are sawed along scribe lines in the [110] direction at the chip edges.