Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
311 words
A semiconductor memory device comprising: one or more upper address bits input terminals through which one or more upper address bits are input; one or more lower address bits input terminals through which one or more lower address bits are input; a regular memory cell array in which a plurality of word lines and bit lines are provided, and a plurality of memory cells are arranged at each intersection of said word lines and bit lines; a redundancy memory cell array in which a plurality of word lines and bit lines are provided, and a plurality of memory cells are arranged at each intersection of said word lines and bit lines, the capacity of said redundancy memory cell array being smaller than that of said regular memory cell array; - a first selection means for selecting a word line or bit line belonging to said regular memory cell array in accordance with said upper address bits and lower address bits; a second selection means for selecting a word line or bit line belonging to said redundancy memory cell array in accordance with said lower address bits; a redundancy address programming means for programming one or more upper address bits included in address data-corresponding tOA defective memory cell existing in said regular memory cell array; and control means for comparing each of said input upper address bits with each of said programmed upper-address bits and for controlling said first and second selection means so that the selection of said word line or bit line belonging to said regular memory cell array is inhibited and a predetermined word line or bit line belonging to said redundancy memory cell array is selected instead of said word line or bit line belonging to said regular memory cell array, when each of said input upper address bits coincides with each of said programmed upper address bits.
Claim 2
Dependent Claim
311 words
A semiconductor memory device comprising: one or more upper address bits input terminals through which one or more upper address bits are input; one or more lower address bits input terminals through which one or more lower address bits are input; a regular memory cell array in which a plurality of word lines and bit lines are provided, and a plurality of memory cells are arranged at each intersection of said word lines and bit lines; a redundancy memory cell array in which a plurality of word lines and bit lines are provided, and a plurality of memory cells are arranged at each intersection of said word lines and bit lines, the capacity of said redundancy memory cell array being smaller than that of said regular memory cell array; - a first selection means for selecting a word line or bit line belonging to said regular memory cell array in accordance with said upper address bits and lower address bits; a second selection means for selecting a word line or bit line belonging to said redundancy memory cell array in accordance with said lower address bits; a redundancy address programming means for programming one or more upper address bits included in address data-corresponding tOA defective memory cell existing in said regular memory cell array; and control means for comparing each of said input upper address bits with each of said programmed upper-address bits and for controlling said first and second selection means so that the selection of said word line or bit line belonging to said regular memory cell array is inhibited and a predetermined word line or bit line belonging to said redundancy memory cell array is selected instead of said word line or bit line belonging to said regular memory cell array, when each of said input upper address bits coincides with each of said programmed upper address bits.
Claim 3
Dependent Claim
92 words
A semiconductor memory device according to claim 1, wherein, said first selection means comprises a first prestage decoder means for decoding said input upper address bits, a second prestage decoder means for decoding said input lower address bits, and a poststage decoder means for inputting and decoding the outputs from said first and second prestage decoder means, and said second selection means comprises a circuit for inputting the output from said second prestage decoder means and for selecting a predetermined word line or bit line belonging to said redundancy memory cell array.
Claim 4
Dependent Claim
71 words
A semiconductor memory device according to claim 2, wherein said control means compares each of said input upper address bits with each of said programmed upper address bits and outputs the control signal for inhibiting the decoding operation of said poststage decoder means and for entering said second selection means into an active state when each of said input upper address bits coincides with each of said programmed upper address bits.
Claim 5
Dependent Claim
56 words
A semiconductor memory device according to claim 1, wherein said first selection means comprises a decoder means for said regular memory cell array for decoding said input upper address bits and lower address bits, and said second selection means comprises a decoder means for said redundancy memory cell array for decoding said input lower address bits.
Claim 6
Dependent Claim
82 words
--5. A semiconductor memory device according to claim 4, wherein said control means compares each of said input upper address bits with each of said programmed upper address bits and outputs the control signal for inhibiting the decoding operation of said decoder means for said regular memory cell array and for entering said decoder means for said redundancy memory cell array into an active state when each of said input upper address bits coincides with each of said programmed upper address bits.
Claim 7
Dependent Claim
22 words
A semiconductor memory device as claimed in any preceding claim wherein said redundancy address programming means is a programmable read-only memory (PROM).
Claim 8
Dependent Claim
39 words
A semiconductor memory device as claimed in any preceding claim wherein said redundancy address programming means stores the upper address bits included in address data of a plurality of defective memory cells existing in the regular memory cell array.