EP0034070A2
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EP
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Fault tolerant memory system
Assignee: CTU of Delaware Inc
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Filing: 1981-02-11
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Granted: —
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Expires: 2001-02-11
Abstract
Abstract lock redundancy is utilized to improve yield and lower die cost for an electrically programmable read only memory (EPROM). The EPROM is organised 8Kx8 with four primary memory blocks 12A, 12B, 12C, 12D on each side of a central row decoder 14. Each block includes an array M of memory cells, column select CS column decode CD, sense amp SA, data buffer DB and other overhead circuitry. One block of redundant circuitry 12RB-1 is also provided for each set of four blocks and includes a redundant memory matrix RM, a redundant column decoder RCD, a redundant column select RCS, a redundant sense amplifier RSA and a redundant data buffer RDB. Incorporated within each primary memory block is a multiplex logic circuit 26 MUX which is independently programmable to selectively disconnect the associated primary memory block and substitute the redundant memory block, including the redundant column decoder, column select, sense amp and data buffer. Each multiplex logic circuit 26 includes a polysilicon fuse which is permanently programmable from a closed to an open circuit condition by applying a high voltage to the external data bit terminal (P1, P2, ...) which corresponds to the defective memory block.
Inventors
- 👤 Vernon George Mckenny
- 👤 David L. Taylor
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 04:23
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
213 words
A fault tolerant memory system comprising a plurality of primary memory blocks having data storage cells arranged in rows and columns and redundant storage cells for replacing defective cells in a memory block, characterised by a redundant memory block (12RB) of data storage cells arranged in rows and columns, data detection means (20) coupled to each primary (12A-B) and redundant (12RB1), memory block, each data detection means each including a data node (36, 40) for separately conducting data from the storage cells of the block to which it is coupled to an external data terminal (Pl, P2, ...) in response to row and column address signals, a plurality of multiplexer circuits (26) each having a first input connected to the data node (36) of the data detection means (20) of a respective primary block and a second input connected to the data node (40) of the data detection means of the redundant block, and an output coupled to the corresponding external terminal (Pl, P2, ...) and independently programmable - means (28) for each multiplexer circuit (26) having a first stable state in which the first input is connected to the multiplexer output and capable of being actuated to a second stable state in which the second input is connected to the multiplexer output.
Claim 2
Dependent Claim
213 words
A fault tolerant memory system comprising a plurality of primary memory blocks having data storage cells arranged in rows and columns and redundant storage cells for replacing defective cells in a memory block, characterised by a redundant memory block (12RB) of data storage cells arranged in rows and columns, data detection means (20) coupled to each primary (12A-B) and redundant (12RB1), memory block, each data detection means each including a data node (36, 40) for separately conducting data from the storage cells of the block to which it is coupled to an external data terminal (Pl, P2, ...) in response to row and column address signals, a plurality of multiplexer circuits (26) each having a first input connected to the data node (36) of the data detection means (20) of a respective primary block and a second input connected to the data node (40) of the data detection means of the redundant block, and an output coupled to the corresponding external terminal (Pl, P2, ...) and independently programmable - means (28) for each multiplexer circuit (26) having a first stable state in which the first input is connected to the multiplexer output and capable of being actuated to a second stable state in which the second input is connected to the multiplexer output.
Claim 3
Dependent Claim
26 words
A fault tolerant memory system according to claim 1, characterised in that each data detection means comprising a sense amplifier (SA) and a data buffer (DB).
Claim 4
Dependent Claim
65 words
A fault tolerant memory system according to claim 2, characterised in that each multiplexer circuit (26) also has an input distributor (IN MUX) with an input connected to the corresponding external terminal (Pl, P2, ...) and first and second outputs enabled in the first and second stable states respectively and connected to the corresponding primary block node (36) and the redundant block node (40) respectively.
Claim 5
Dependent Claim
74 words
A fault tolerant memory system according to claim 1, 2 or 3, characterised in that each independently programmable means (28) comprising a repair buffer (28) including a polycrystalline silicon fuse (30) and a gate circuit (Q7-Q9) coupled to the fuse for conducting heavy current flow through the fuse in response to a repair signal (RPR) applied to the gate circuit and a programming voltage applied to the corresponding external data pin (Pl, P2, ...).
Claim 6
Dependent Claim
149 words
A fault tolerant memory system according to any of claims 1 to 4, characterised in that each multiplexer circuit (26) includes first and second gate circuits (Q5 and Q10) connected in series between the output nodes (36 and 40) of the corresponding primary memory block and redundant block respectively, and the corresponding external data terminal (Pl, P2 ...) and that each independently programmable means (28) includes a fuse (30) and a switching . circuit (Q1-Q4) coupled to the fuse, the switching circuit having first and second output nodes (50 and 48) coupled to the first and second multiplexer gate circuits (Q5 and Q10) respectively, the switching circuit developing enable and complement enable signals on the first and second output nodes respectively, when the fuse is intact and developing complement enable and enable signals on the first and second output nodes respectively, when the fuse is in open circuit condition.
Claim 7
Dependent Claim
185 words
A fault tolerant memory system, characterised by the combination of a plurality of primary memory blocks each including a plurality of rows and columns of data storage cells; a redundant memory block including a plurality of rows and columns of data storage cells; cell selection means coupled to each primary and redundant memory block for simultaneously addressing a cell at identical row and-column addresses in each block; data detection means coupled to each cell selection means having a data node separately conducting data to one of a plurality of external data terminals; each multiplexer having first and second control inputs, first and second data inputs, and a common data output, the first and second data inputs being connected to the data node of the primary block data detection means and to the data output node of the redundant block data detection means respectively, and the common data output being coupled to the corresponding primary block external data terminal; and independently programmable means coupled to each multiplexer for logically enabling data transmission exclusively from the corresponding primary memory block or exclusively from the redundant memory block.
Claim 8
Dependent Claim
185 words
A fault tolerant memory system, characterised by the combination of a plurality of primary memory blocks each including a plurality of rows and columns of data storage cells; a redundant memory block including a plurality of rows and columns of data storage cells; cell selection means coupled to each primary and redundant memory block for simultaneously addressing a cell at identical row and-column addresses in each block; data detection means coupled to each cell selection means having a data node separately conducting data to one of a plurality of external data terminals; each multiplexer having first and second control inputs, first and second data inputs, and a common data output, the first and second data inputs being connected to the data node of the primary block data detection means and to the data output node of the redundant block data detection means respectively, and the common data output being coupled to the corresponding primary block external data terminal; and independently programmable means coupled to each multiplexer for logically enabling data transmission exclusively from the corresponding primary memory block or exclusively from the redundant memory block.
Claim 9
Dependent Claim
171 words
A memory system of the type including a primary memory block having data storage cells arranged in rows and columns and cell selection/data detection circuitry for conducting data from the cells to an external data terminal, characterised by a redundant memory block having data storage cells arranged in rows and columns and cell selection/data detection circuitry for conducting data from the cells of the redundant blocks; a multiplexer interposed between the primary memory block, the redundant memory block and the external data pin for selectively enabling the transmission of data exclusively from the primary memory block or exclusively from the redundant memory block to the external data terminal; arid independently programmable means coupled to the multiplexer for controlling its operation, said programmable means being characterized by first and second programmable stable states, wherein data transmission from the primary memory block to the external data pin is enabled in response to the first stable state, and data transmission from the redundant memory block being enabled in response to the second stable state.
Claim 10
Dependent Claim
171 words
A memory system of the type including a primary memory block having data storage cells arranged in rows and columns and cell selection/data detection circuitry for conducting data from the cells to an external data terminal, characterised by a redundant memory block having data storage cells arranged in rows and columns and cell selection/data detection circuitry for conducting data from the cells of the redundant blocks; a multiplexer interposed between the primary memory block, the redundant memory block and the external data pin for selectively enabling the transmission of data exclusively from the primary memory block or exclusively from the redundant memory block to the external data terminal; arid independently programmable means coupled to the multiplexer for controlling its operation, said programmable means being characterized by first and second programmable stable states, wherein data transmission from the primary memory block to the external data pin is enabled in response to the first stable state, and data transmission from the redundant memory block being enabled in response to the second stable state.
References Cited (Backward Citations)
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