Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
158 words
A multiple computer system having a plurality of computer stations each executing a control program and which use a common data bus in a time-share mode to transfer data among the input/output circuits of the computer stations, at least one computer station comprising: (a) means for commanding a data input/output circuit of the computer station to output a predetermined coded pulse train signal before executing the control program; (b) means for judging whether the predetermined coded pulse from the data input/output circuit is correct; and (c) means for disconnecting the computer station from the common data bus while the predetermined coded pulse train signal is outputted from the data input/output circuit and when said judging means judges that the predetermined coded pulse is not correct and connecting the computer station to the common data bus only when said judging means judges that the predetermined coded pulse is correctly outputted from the data input/output circuit of the computer station.
Claim 2
Dependent Claim
158 words
A multiple computer system having a plurality of computer stations each executing a control program and which use a common data bus in a time-share mode to transfer data among the input/output circuits of the computer stations, at least one computer station comprising: (a) means for commanding a data input/output circuit of the computer station to output a predetermined coded pulse train signal before executing the control program; (b) means for judging whether the predetermined coded pulse from the data input/output circuit is correct; and (c) means for disconnecting the computer station from the common data bus while the predetermined coded pulse train signal is outputted from the data input/output circuit and when said judging means judges that the predetermined coded pulse is not correct and connecting the computer station to the common data bus only when said judging means judges that the predetermined coded pulse is correctly outputted from the data input/output circuit of the computer station.
Claim 3
Dependent Claim
42 words
A multiple computer system according to claim 1, wherein said commanding means commands the data input/ output circuit to output an enable signal together with the .predetermined coded signal to enable said judging means to input the predetermined coded pulse train signal.
Claim 4
Dependent Claim
156 words
A multiple computer system according to claim 2, wherein said judging means comprises; (a) an AND gate which conducts the predetermined coded pulse train signal only when the enable signal is received; (b) first means for producing a first pulse signal having a first predetermined duration in response to receipt of the predetermined coded pulse signal from said AND gate; (c) a shift register which receives the predetermined ceded pulse train signal from said AND gate upon receipt of the enable signal from said commanding means, shifts one bit each time one pulse of the predetermined coded pulse signal is inputted, and sets the currently-shifted bit when the pulse width of the received pulse of the coded pulse signal exceeds that of the first pulse signal from said first means; and (d) a sign detector which outputs a second pulse signal only when the bit values of said shift register match a predetermined bit. code pattern.
Claim 5
Dependent Claim
146 words
A multiple computer system according to claim 3, wherein said disconnecting means comprises; (a) a reset circuit which produces a third pulse signal for resetting the computer unit at a predetermined time after power is first supplied to the computer station; (b) second means for producing a fourth pulse signal having a short pulse width upon receipt of the third pulse signal; (c) a flip-flop circuit, the reset terminal of which is connected to said second means and the set terminal of which is connected to' said sign detector of said judging means, for producing a fifth pulse signal only when the second pulse signal is received from said sign detector; and (d) a switching circuit, connected between the data input/output circuit Q f the computer station and the common data bus, which turns on when the fifth pulse signal is produced by said flip-flop circuit.
Claim 6
Dependent Claim
35 words
A multiple computer system according to claim 4, wherein the predetermined coded pulse signal has at-least one pulse having a pulse width shorter than that of the first pulse signal outputted from said first means.
Claim 7
Dependent Claim
16 words
A multiple computers system according to claim 3, wherein said .first means is a monostable multivibrator.
Claim 8
Dependent Claim
16 words
A multiple computers system according to claim 4, wherein said second means is a monostable multivibrator.