EP0054692A2
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EP
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Memory testing apparatus
Assignee: International Business Machines Corp
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Filing: 1981-10-27
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Granted: —
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Expires: 2001-10-27
Abstract
Abstract A testing apparatus, having an address generator for providing address signals to a test memory and to a reference memory, is provided with a programmable mask for passing only selected least significant X and Y address bits to the reference memory.
Inventors
- 👤 Robert E. Jones
- 👤 Donald H. Wood
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 17:19
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
126 words
A testing apparatus of the type including a standard memory for providing an output in response to N address signals received on N address input lines, a test device for providing an output in response to address signals received on a plurality of address lines, an address generator for providing address signals to said standard and test devices, and means for comparing the outputs from said two devices, characterized in that said address generating means (18) provides M address signals on M address output lines, M>N, in that programmable masking means (22) are provided for selecting N of said M .address signals to be supplied as the N address signals to said standard device, and in that the test memory (16) only accepts N address signals.
Claim 2
Dependent Claim
126 words
A testing apparatus of the type including a standard memory for providing an output in response to N address signals received on N address input lines, a test device for providing an output in response to address signals received on a plurality of address lines, an address generator for providing address signals to said standard and test devices, and means for comparing the outputs from said two devices, characterized in that said address generating means (18) provides M address signals on M address output lines, M>N, in that programmable masking means (22) are provided for selecting N of said M .address signals to be supplied as the N address signals to said standard device, and in that the test memory (16) only accepts N address signals.
Claim 3
Dependent Claim
53 words
A testing apparatus as defined in claim 1, wherein said programmable masking means (22) comprises: a plurality of gates (30) each of which passes an address signal (X,Y) from said address generator (18) in response to a respective enabling signal (EN); and means for selectively providing enabling signals to said plurality of gates.
Claim 4
Dependent Claim
92 words
A testing apparatus as defined in claim 2, wherein said address generator (18) provides a plurality of X address signals and a plurality Y address signals and said plurality of gates (30) are connected in pairs with one gate in each pair receiving a respective X address signal from said address generator and one gate in each pair receiving a Y address signal from said address generator, the outputs of the gates in each pair being coupled together to provide one of said N address signals (A) to said standard device (14).
Claim 5
Dependent Claim
54 words
A testing apparatus as defined in claim 3, wherein said gates (30) are tri-state gates and a pull-up resistor (34) is coupled to the outputs of each gate pair whereby the address signal (A) provided by said gate pair will assume a known value when neither of the gates in said pair is enabled.
Claim 6
Dependent Claim
68 words
A testing apparatus as defined in claim 3, wherein said X address signals are designated X 0 - X 1 and said Y address signals are designated Y 0 - Y 1 , and said X and Y address signals are paired in reverse numerical order with signals X 0 - X 1 being combined in said gate pairs with signals Y 1 - Y 0 , respectively.
Claim 7
Dependent Claim
20 words
A testing apparatus as defined in claim 3, wherein said gates are emitter coupled logic (ECL) gates having dottable outputs.
Claim 8
Dependent Claim
31 words
A testing apparatus as defined in claim 3, further comprising fault indicating AND logic means (32) for providing an output signal when both gates in any one gate pair are enabled.
Claim 9
Dependent Claim
73 words
A testing apparatus as defined in any one of claims 2-7, wherein said means for selectively providing said enabling signals comprises: latch means (50, 56) for receiving enabling data and storing said enabling data in response to a load signal (54, 58), said latch means providing enabling signals (EN) at its output in accordance with said enabling data; and control means (52) for providing said data and load signals to said latch means.
References Cited (Backward Citations)
No citation records indexed.
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