Patent EP0378450A2 successfully refreshed from Google Patents.
USH1035H
Expired / Lapsed
US
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Non-volatile analog memory circuit with closed-loop control
Assignee: United States Department of the Navy
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Filing: 1990-06-20
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Granted: 1992-03-03
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Expires: 2010-06-20
Abstract
Abstract A non-volatile analog memory circuit includes charge depositing and storingircuitry, voltage sensing circuitry, and closed-loop control circuitry. The charge depositing and storing circuitry includes a floating gate operable to receive charge deposited on it. The voltage sensing circuitry supplies an analog output in response to the sensed gate potential. The closed-loop control circuitry is used to control charge deposition. The control circuitry is operable to change the charge on the gate by directing electrical pulses of appropriate polarity to the charge depositing and storing circuitry. This is done to diminish the error between the analog output signal of the charge sensing circuitry and an analog input signal for providing a substantially accurate representation of the analog input signal.
Inventors
- 👤 Gene L. Haviland
- 👤 Patrick A. Shoemaker
- 👤 James R. Feeley
- 👤 Alfons Tuszynski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:48
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/30; H03F1/303; G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
111 words
A non-volatile analog memory circuit comprising: (a) charge depositing and storing circuitry including a memory cell having a floating gate capable of storing electrical charge, said circuitry being operable in a manner which allows either an increment or decrement to be made to stored charge on said memory cell; (b) charge sensing circuitry operably coupled to said memory cell and including said floating gate as a part thereof and in response to the charge on said memory cell supplying an analog output signal representative of the stored charge; and (c) closed-loop control circuitry for controlling operation of said charge depositing and storing circuitry by deposition of charge on said memory cell.
Claim 2
Dependent Claim
111 words
A non-volatile analog memory circuit comprising: (a) charge depositing and storing circuitry including a memory cell having a floating gate capable of storing electrical charge, said circuitry being operable in a manner which allows either an increment or decrement to be made to stored charge on said memory cell; (b) charge sensing circuitry operably coupled to said memory cell and including said floating gate as a part thereof and in response to the charge on said memory cell supplying an analog output signal representative of the stored charge; and (c) closed-loop control circuitry for controlling operation of said charge depositing and storing circuitry by deposition of charge on said memory cell.
Claim 3
Dependent Claim
67 words
The circuit of claim 1 wherein said control circuitry is operable to change the charge on said memory cell in order to diminish any difference between the analog output signal of said charge sensing circuitry and an analog input signal to said closed loop control circuitry, for providing a substantially accurate representation of the analog input signal by means of the charge stored upon said memory cell.
Claim 4
Dependent Claim
39 words
The circuit of claim 2 wherein said charge depositing and storing circuitry includes a pair of writing devices operably coupled with said memory cell and each being operable in a charge-injecting mode to deposit charge on said memory cell.
Claim 5
Dependent Claim
22 words
The circuit of claim 3 wherein said writing devices are a pair of complementary metal-oxide-silicon (CMOS) transistors including said common floating gate.
Claim 6
Dependent Claim
35 words
The circuit of claim 4 wherein said control circuitry is operable to change the charge on said floating gate by directing at least one electrical pulse to a respective one of said charge-injecting MOS transistors.
Claim 7
Dependent Claim
33 words
The circuit of claim 2 wherein said control circuitry is operable to change the charge on said memory cell by directing at least one electrical pulse to said charge depositing and storing circuitry.
Claim 8
Dependent Claim
176 words
The circuit of claim 6 wherein said control circuitry includes: subtracting circuitry having a first and a second input each for receiving analog signals and an output and being operable to produce an analog error signal on said output thereof proportional to a difference between said analog signal supplied on said second input and said analog input supplied on said first input; pulsing circuitry connected between said subtracting circuitry and said charge depositing and storing circuitry; and feedback circuitry connecting an output of said charge sensing circuitry with said first input of said subtracting circuitry such that when an analog value is to be set in said memory cell, the desired analog value in the form of an analog input signal is applied to said second input of said subtracting circuitry and said analog output signal of said charge sensing circuitry is applied to said first input of said subtracting circuitry whereupon in response to the application of said analog input and output signals, said substracting circuitry supplies said analog error signal to said pulsing circuitry.
Claim 9
Dependent Claim
152 words
The circuit of claim 7 wherein said pulsing circuitry in response to receipt of said analog error signal is operable to perform one of the following actions based on the following conditions: (i) if the absolute value of said analog error signal is less than a predetermined acceptable error value, then no pulse is applied to said charge depositing and storing circuitry; (ii) if said analog error signal is greater than said predetermined acceptable error value, then one or more pulses are applied to said charge depositing and storing circuit so as to increase said analog output signal until the condition of (i) is met; or (iii) if said analog error signal is less than the negative of said predetermined acceptable error value, then one or more pulses are applied to said charge depositing and storage circuitry so as to decrease said analog output signal until the condition of (i) is met.
Claim 10
Dependent Claim
47 words
The circuit of claim 7 wherein: said analog error signal is a monotonic function of the difference between said analog input and output signals for causing operation of said pulsing circuitry in controlling said charge depositing and storing circuitry in setting the charge on said memory cell.
Claim 11
Dependent Claim
26 words
The circuit of claim 2 wherein said charge depositing and storing circuitry comprises a double gate structure wherein one of said gates is a floating gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-03 | 1995-09-02 | 1996-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-03 | 1999-09-02 | 2000-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-03 | 2003-09-02 | 2004-03-03 | $7700.00 | Window Closed / Lapsed |