Analogue memory device

Claim 2

An analogue memory device comprising: means for alternately applying a writing pulse and an input analogue information pulse to be memorized to a nonvolatile memory element; means for detecting by comparison whether the memorized analogue information pulse in the memory element is as large in value as the input analogue information pulse; means for halting the operation of applying the writing pulse and input analogue information pulse to the memory element when the memorized analogue information pulse is as large in value as the input analogue information pulse.

Claim 3

An analogue memory device according to claim 1 wherein the nonvolatile memory element is a nonvolatile insulated gate type field effect transistor two insulatoR layers therein to store a charge therebetween.

Claim 4

An analogue memory device according to claim 1, wherein the nonvolatile memory element is a MNOS transistor.

Claim 5

An analogue memory device according to claim 1, wherein the nonvolatile memory element is a MAOS transistor.

Claim 6

An analogue memory device according to claim 1, wherein the nonvolatile element is a magnetic memory.

Claim 7

An analogue memory device comprising: a nonvolatile insulated gate field effect memory transistor having a source, a drain and an insulated gate; a first insulated gate field effect transistor having a source, a drain and an insulated gate; a second insulated gate field effect transistor having a source, a drain and an insulated gate; means connecting the source of the first insulated gate field effect transistor to the gate of the memory transistor; means for applying a writing pulse to the drain of the first insulated gate field effect transistor; means for applying an input analogue information pulse to be memorized to the source of the second insulated gate field effect transistor; means connecting the drain of the second insulated gate field effect transistor to the gate of memory transistor and a detecting circuit connected to the source of the memory transistor for detecting whether the memorized analogue information pulse in the memory transistor is as large in value as the input analogue information pulse.

Claim 8

An analogue memory device comprising: a nonvolatile insulated gate field effect memory transistor having a source, a drain and an insulated gate; a first insulated gate field effect transistor having a source, a drain and an insulated gate; a second insulated gate field effect transistor having a source, a drain and an insulated gate; means connecting the source of the first insulated gate field effect transistor to the gate of the memory transistor; means for applying a writing pulse to the drain of the first insulated gate field effect transistor; means for applying an input analogue information pulse to be memorized to the source of the second insulated gate field effect transistor; means connecting the drain of the second insulated gate field effect transistor to the gate of memory transistor and a detecting circuit connected to the source of the memory transistor for detecting whether the memorized analogue information pulse in the memory transistor is as large in value as the input analogue information pulse.

Claim 9

An analogue memory device according to claim 6 further comprising: a reading voltage generating circuit; a third insulated gate field effect transistor having a source, a drain and an insulated gate; means connecting the drain of the third insulated gate field effect transistor to an output of the reading voltage generating circuit; means connecting the source of the third insulated gate field effect transistor to the gate of the memory transistor and an output circuit connected to an output of the detecting circuit for generating an output signal.

Claim 10

An analogue memory device according to claim 6 further comprising: an erasing circuit connected to the source of the memory transistor.

Claim 11

An analogue memory device according to claim 6 in which the memory transistor comprises several nonvolatile insulated gate field effect memory transistors arranged in an array.

Claim 12

An analogue memory device according to claim 9 further comprising means for selecting one of the memory transistors arranged in an array.

Claim 13

An analogue memory device according to claim 9, in which the memory transistor array is integrated into a semiconductor wafer.