Non-volatile random access memory cell with CMOS transistors having a common floating grid

Claim 1

A non-volatile memory cell, incorporating a bistable flip-flop with two complementary outputs supplied by a d.c. voltage, having a non-volatile storage element, wherein said element is connected between the two complementary outputs of the flip-flop and has a series arrangement of two complementary MOS transistors, namely a n channel transistor and a p channel transistor, said two transistors having a common floating grid covering their channel regions and insulated therefrom by a first thin insulating layer, and a common control grid covering the floating grid and insulated therefrom by a second thin insulating layer, the first insulating layer having a thin injection zone on the side of the source region of one of the complementary transistors said source region being connected to a first output of the flip-flop, whilst the control grid is connected to the second output, said cell also having means for temporarily applying a supply potential to the junction point of the two complementary transistors.