US9064928B2
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Growth of multi-layer group III-nitride buffers on large-area silicon substrates and other substrates
Assignee: National Semiconductor Corp
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Filing: 2013-10-22
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Granted: 2015-06-23
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Expires: 2033-10-22
Abstract
Abstract A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.
Inventors
- 👤 Sandeep R. Bahl
- 👤 Jamal Ramdani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:17
CPC Classifications
H01L21/762; H; H10; H10W; H10W10/00; H10W10/10; H01L21/0237; H01L21/02381; H01L21/02458; H01L21/02502; H01L21/0254; H01L21/02639; H01L21/7605; H01L29/0649; H01L29/1075; H01L29/2003; H01L29/205; H01L29/66462; H01L29/7787; H10D; H10D30/00; H10D30/01; H10D30/015; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D30/4755; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/17; H10D62/351; H10D62/357; H10D62/80; H10D62/82; H10D62/824; H10D62/85; H10D62/8503; H10P; H10P14/00; H10P14/20; H10P14/27; H10P14/271; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/32; H10P14/3202; H10P14/3214; H10P14/3216; H10P14/3242; H10P14/3244; H10P14/3248; H10P14/34; H10P14/3402; H10P14/3414; H10P14/3416; H10W10/01; H10W10/011; H01L23/485; H01L27/0605; H01L27/088; H01L2924/00; H01L2924/0002; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/80; H10D84/82; H10D84/83; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
148 words
A system comprising: a semiconductor substrate comprised of a material selected from the group of silicon, sapphire, or silicon carbide; a nucleation layer formed over the substrate composed of aluminum nitride; a buffer layer formed over the nucleation layer, comprising a plurality of separated first epitaxial regions wherein, the plurality of separated first epitaxial regions form isolated component islands wherein, the component islands are configured to provide a starting surface structured to minimize dislocations; at least one Group III-nitride second epitaxial layer formed over the buffer layer wherein, the Group III-nitride layer is configured to form a device layer having a portion of a semiconductor device; the portion of the device layer doped with one or more dopants to form a source, a drain, or other transistor regions; and one or more conductive layers formed over the transistor region, patterned and etched to form source and drain contacts.
Claim 2
Independent Claim
148 words
A system comprising: a semiconductor substrate comprised of a material selected from the group of silicon, sapphire, or silicon carbide; a nucleation layer formed over the substrate composed of aluminum nitride; a buffer layer formed over the nucleation layer, comprising a plurality of separated first epitaxial regions wherein, the plurality of separated first epitaxial regions form isolated component islands wherein, the component islands are configured to provide a starting surface structured to minimize dislocations; at least one Group III-nitride second epitaxial layer formed over the buffer layer wherein, the Group III-nitride layer is configured to form a device layer having a portion of a semiconductor device; the portion of the device layer doped with one or more dopants to form a source, a drain, or other transistor regions; and one or more conductive layers formed over the transistor region, patterned and etched to form source and drain contacts.
Claim 3
Dependent Claim
33 words
The system of claim 1 , wherein the at least one Group III-nitride device layer comprises multiple separated second epitaxial regions, the second epitaxial regions substantially formed only on the first epitaxial regions.
Claim 4
Dependent Claim
28 words
The system of claim 1 , wherein the second epitaxial layer comprises epitaxial material that covers the first epitaxial regions and at least a portion of the substrate.
Claim 5
Dependent Claim
44 words
The system of claim 1 , wherein: the second epitaxial layer comprises multiple separated second epitaxial regions; and the system further comprises multiple dielectric regions electrically separating the first epitaxial regions from one another and electrically separating the second epitaxial regions from one another.
Claim 6
Dependent Claim
32 words
The system of claim 1 , further comprising: an isolation region in the device layer and at least a portion of the buffer, the isolation region configured to isolate the semiconductor device.
Claim 7
Dependent Claim
87 words
The system of claim 1 , wherein: the substrate comprises a <111> silicon wafer having a diameter of at least six inches; the at least one Group III-nitride comprises one or more of: gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), indium aluminum gallium nitride (InAlGaN), aluminum nitride (AlN), indium nitride (InN), and indium gallium nitride (InGaN); the first epitaxial layer has a thickness of 1 μm to 3 μm; and the second epitaxial layer has a thickness of 1 μm to 3 μm.
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