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US7301205B2 Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device and method of manufacturing the same

Assignee: Toshiba Corp
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Filing: 2005-06-16
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Granted: 2007-11-27
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Expires: 2025-06-16
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Abstract

Abstract According to an aspect of the invention, there is provided a semiconductor device provided with a CMOS-FET circuit, comprising at least one of a tensile stress film disposed in a part of an element isolating film around an NMOS forming region and having a tensile stress, and a compressive stress film disposed in a part of an element isolating film around a PMOS forming region and having a compressive stress.

Inventors

  • 👤 Hisakazu Matsumori

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 22:18
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/791; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/0188; H10D84/02; H10D84/03; H10D84/038

Claims Analysis

Total Claims: 24
Claim 1
Independent Claim 162 words
A semiconductor device provided with a CMOS-FET circuit, comprising: a first element isolating film filling a trench provided around an NMOS forming region; a second element isolating film filling a trench provided around a PMOS forming region; a first insulating film provided on the first and second element isolating films; a second insulating film provided on the first insulating film; a tensile stress film provided on the second insulating film, penetrating the first and second insulating films, extending into the first element isolating film, and having a tensile stress, the tensile stress film having an end; and a compressive stress film provided on the second insulating film, penetrating the first and second insulating film, extending into the second element isolating film, and having a compressive stress, the compressive stress film having an end; wherein the end of the tensile stress film contacts the end of the compressive stress film above a region between the NMOS forming region and the PMOS forming region.
Claim 2
Dependent Claim 162 words
A semiconductor device provided with a CMOS-FET circuit, comprising: a first element isolating film filling a trench provided around an NMOS forming region; a second element isolating film filling a trench provided around a PMOS forming region; a first insulating film provided on the first and second element isolating films; a second insulating film provided on the first insulating film; a tensile stress film provided on the second insulating film, penetrating the first and second insulating films, extending into the first element isolating film, and having a tensile stress, the tensile stress film having an end; and a compressive stress film provided on the second insulating film, penetrating the first and second insulating film, extending into the second element isolating film, and having a compressive stress, the compressive stress film having an end; wherein the end of the tensile stress film contacts the end of the compressive stress film above a region between the NMOS forming region and the PMOS forming region.
Claim 3
Dependent Claim 145 words
A semiconductor device provided with a CMOS-FET circuit, comprising: a first element isolating film filling a trench provided around an NMOS forming region; a second element isolating film filling a trench provided around a PMOS forming region; a first insulating film provided on the first and second element isolating films; a second insulating film provided on the first insulating film; a tensile stress film provided on the second insulating film, penetrating the first and second insulating film, extending into the first element isolating film, and having a tensile stress, the tensile stress film having an end; and a compressive stress film provided on the second insulating film, penetrating the first and second insulating film, extending into the second element isolating film, and having a compressive stress; wherein the end of the tensile stress film contacts the compressive stress film above the first element isolating film.
Claim 4
Dependent Claim 145 words
A semiconductor device provided with a CMOS-FET circuit, comprising: a first element isolating film filling a trench provided around an NMOS forming region; a second element isolating film filling a trench provided around a PMOS forming region; a first insulating film provided on the first and second element isolating films; a second insulating film provided on the first insulating film; a tensile stress film provided on the second insulating film, penetrating the first and second insulating film, extending into the first element isolating film, and having a tensile stress, the tensile stress film having an end; and a compressive stress film provided on the second insulating film, penetrating the first and second insulating film, extending into the second element isolating film, and having a compressive stress; wherein the end of the tensile stress film contacts the compressive stress film above the first element isolating film.
Claim 5
Dependent Claim 28 words
The semiconductor device according to claim 1 , wherein the tensile stress film is a silicon nitride film formed by a reduced-pressure CVD process using dichlorosilane and ammonia.
Claim 6
Dependent Claim 25 words
The semiconductor device according to claim 2 , wherein the tensile stress film is an alloy film containing at least one of titanium and tungsten.
Claim 7
Dependent Claim 28 words
The semiconductor device according to claim 1 , wherein the compressive stress film is a silicon nitride film formed by a plasma CVD process using monosilane and ammonia.
Claim 8
Dependent Claim 19 words
The semiconductor device according to claim 1 , wherein the tensile stress film surrounds an NMOS type active area.
Claim 9
Dependent Claim 25 words
The semiconductor device according to claim 6 , wherein the tensile stress film surrounds the side surface and the upper surface of the active area.
Claim 10
Dependent Claim 19 words
The semiconductor device according to claim 1 , wherein the compressive stress film surrounds a PMOS type active area.
Claim 11
Dependent Claim 25 words
The semiconductor device according to claim 8 , wherein the compressive stress film surrounds the side surface and the upper surface of the active area.
Claim 12
Independent Claim 184 words
A method of manufacturing a semiconductor device provided with a CMOS-FET circuit, comprising: forming a first element isolating film filling a trench around an NMOS forming region on a semiconductor substrate; forming a second element isolating film filling a trench around a PMOS forming region on the semiconductor substrate; forming a first insulating film on the first and second element isolating films; forming a second insulating film on the first insulating film; forming a first trench penetrating the first and second insulating films and extending into the first element isolating film; forming a tensile stress film in the first trench and on the second insulating film, the tensile stress film having an end; forming a second trench penetrating the first and second insulating films and extending into the second element isolating film; and forming a compressive stress film in the second trench and on the second insulating film, the compressive stress film having an end; wherein the end of the tensile stress film contacts the end of the compressive stress film above a region between the NMOS forming region and the PMOS forming region.
Claim 13
Independent Claim 184 words
A method of manufacturing a semiconductor device provided with a CMOS-FET circuit, comprising: forming a first element isolating film filling a trench around an NMOS forming region on a semiconductor substrate; forming a second element isolating film filling a trench around a PMOS forming region on the semiconductor substrate; forming a first insulating film on the first and second element isolating films; forming a second insulating film on the first insulating film; forming a first trench penetrating the first and second insulating films and extending into the first element isolating film; forming a tensile stress film in the first trench and on the second insulating film, the tensile stress film having an end; forming a second trench penetrating the first and second insulating films and extending into the second element isolating film; and forming a compressive stress film in the second trench and on the second insulating film, the compressive stress film having an end; wherein the end of the tensile stress film contacts the end of the compressive stress film above a region between the NMOS forming region and the PMOS forming region.
Claim 14
Independent Claim 168 words
A method of manufacturing a semiconductor device provided with a CMOS-FET circuit, comprising: forming a first element isolating film filling a trench around an NMOS forming region on a semiconductor substrate; forming a second element isolating film filling a trench around a PMOS forming region on the semiconductor substrate; forming a first insulating film on the first and second element isolating films; forming a second insulating film on the first insulating film; forming a first trench penetrating the first and second insulating films and extending into the first element isolating film; forming a tensile stress film in the first trench and on the second insulating film, the tensile stress film having an end; forming a second trench penetrating the first and second the insulating films and extending into the second element isolating film; and forming a compressive stress film in the second trench and on the second insulating film; wherein the end of the tensile stress film contacts the compressive stress film above the first element isolating film.
Claim 15
Independent Claim 168 words
A method of manufacturing a semiconductor device provided with a CMOS-FET circuit, comprising: forming a first element isolating film filling a trench around an NMOS forming region on a semiconductor substrate; forming a second element isolating film filling a trench around a PMOS forming region on the semiconductor substrate; forming a first insulating film on the first and second element isolating films; forming a second insulating film on the first insulating film; forming a first trench penetrating the first and second insulating films and extending into the first element isolating film; forming a tensile stress film in the first trench and on the second insulating film, the tensile stress film having an end; forming a second trench penetrating the first and second the insulating films and extending into the second element isolating film; and forming a compressive stress film in the second trench and on the second insulating film; wherein the end of the tensile stress film contacts the compressive stress film above the first element isolating film.
Claim 16
Dependent Claim 20 words
The method according to claim 10 , wherein the tensile stress film is further formed above the NMOS forming region.
Claim 17
Dependent Claim 20 words
The method according to claim 10 , wherein the compressive stress film is further formed above the PMOS forming region.
Claim 18
Dependent Claim 37 words
The method according to claim 10 , further comprising patterning a resist film on a part of the element isolating film around the NMOS forming region or the PMOS forming region, when the first trench is formed.
Claim 19
Dependent Claim 24 words
The method according to claim 14 , wherein the resist film is patterned in parallel with a gate structure pattern on the semiconductor substrate.
Claim 20
Dependent Claim 27 words
The method according to claim 14 , wherein the resist film is patterned perpendicular to a long dimension of a gate structure pattern on the semiconductor substrate.
Claim 21
Dependent Claim 32 words
The method according to claim 12 , wherein a film thickness of the tensile stress film above the NMOS forming region is substantially equal to a short-side width of the first trench.
Claim 22
Dependent Claim 32 words
The method according to claim 13 , wherein a film thickness of the compressive stress film above the PMOS forming region is substantially equal to a short-side width of the second trench.
Claim 23
Dependent Claim 16 words
The method according to claim 10 , wherein the semiconductor substrate is a bulk Si substrate.
Claim 24
Dependent Claim 15 words
The method according to claim 10 , wherein the semiconductor substrate is an SOI substrate.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2010-11-26 2011-05-28 2011-11-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2014-11-26 2015-05-28 2015-11-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2018-11-26 2019-05-28 2019-11-27 $7700.00 Window Closed / Lapsed

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