US7536597B2
Expired / Lapsed
US
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Apparatus and method for controlling power, clock, and reset during test and debug procedures for a plurality of processor/cores
Assignee: Texas Instruments Inc
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Filing: 2006-04-26
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Granted: 2009-05-19
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Expires: 2026-04-26
Abstract
Abstract An interface unit is provided for use with a JTAG test and debug procedure involving a plurality of processor cores. The interface unit is provided with a logic unit that can translate test and debug commands into control signals. The control signals are applied to a power state machine coupled to a processor/core. The state of the power state machine can thereby be controlled and therefore the parameters of the associated processor/core, i.e., the power and clock parameters of the processor/core. In addition, the logic unit can generate control signals for activating switches, switches that controllably selective apply the TRST signal and the TMS signal to the TAP unit of the processor/core. This capability permits the TAP units of each processor/core to be synchronized.
Inventors
- 👤 Robert A. McGowan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:36
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06F11/2242; G06F11/28; G06F1/00; G06F1/04; G06F11/26; G06F11/261; G06F9/00; G06F9/06; G06F9/30
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
121 words
An apparatus comprising: a plurality of processor cores, wherein each processor core is coupled to a respective one power state machine of a plurality of power state machines, wherein each power state machine is configured to control power and clock parameters of the respective processor core, and wherein each processor core comprises a test access port (TAP); and an interface unit coupled to the plurality of power state machines, wherein the interface unit comprises a TAP configured to receive test commands, and wherein the interface unit is configured to selectively provide control signals to the plurality of power state machines to force a parameter change in the respective processor cores in response to a received test command requesting the parameter change.
Claim 2
Independent Claim
121 words
An apparatus comprising: a plurality of processor cores, wherein each processor core is coupled to a respective one power state machine of a plurality of power state machines, wherein each power state machine is configured to control power and clock parameters of the respective processor core, and wherein each processor core comprises a test access port (TAP); and an interface unit coupled to the plurality of power state machines, wherein the interface unit comprises a TAP configured to receive test commands, and wherein the interface unit is configured to selectively provide control signals to the plurality of power state machines to force a parameter change in the respective processor cores in response to a received test command requesting the parameter change.
Claim 3
Dependent Claim
27 words
The apparatus of claim 1 , wherein the interface unit is further configured to store current parameters of each processor core of the plurality of processor cores.
Claim 4
Dependent Claim
43 words
The apparatus of claim 1 , wherein the interface unit is further configured to, in response to a received test command, communicate current parameters of at least one processor core to a test and debug unit using the TAP of the interface unit.
Claim 5
Dependent Claim
27 words
The apparatus of claim 1 , wherein each power state machine is further configured to confirm to the interface unit that a requested parameter change is completed.
Claim 6
Dependent Claim
122 words
The apparatus of claim 1 , further comprising: a plurality of switch units, wherein each switch unit is coupled to the TAP of a respective one processor core of the plurality of processor cores, and wherein each switch unit is coupled to receive a test signal from a test and debug unit, and wherein the interface unit is coupled to the plurality of switch units to selectively provide control signals to the plurality of switch units, and wherein the interface unit is further configured to, in response to a received test command, selectively provide control signals to at least one of the switch units to cause the at least one switch unit to apply the received test signal to the respective TAP.
Claim 7
Dependent Claim
15 words
The apparatus of claim 5 , wherein the test signal is a JTAG test signal.
Claim 8
Dependent Claim
32 words
The apparatus of claim 5 , wherein the test signal is one selected from a group consisting of a JTAG test reset signal (TRST) and a JTAG test mode select (TMS) signal.
Claim 9
Dependent Claim
17 words
The apparatus of claim 1 , wherein the plurality of processor cores are on a same substrate.
Claim 10
Dependent Claim
110 words
method comprising: receiving a test command in a test access port (TAP) of an interface unit coupled to a plurality of power state machines, wherein each power state machine is coupled to a respective one processor core of a plurality of processor cores to control power and clock parameters of the respective one processor core, wherein each processor core comprises a TAP, and wherein the test command requests a parameter change in at least one processor core of the plurality of processor cores; and sending, by the interface unit, control signals to the power state machine coupled to the at least one processor core, wherein the parameter change is forced.
Claim 11
Dependent Claim
110 words
method comprising: receiving a test command in a test access port (TAP) of an interface unit coupled to a plurality of power state machines, wherein each power state machine is coupled to a respective one processor core of a plurality of processor cores to control power and clock parameters of the respective one processor core, wherein each processor core comprises a TAP, and wherein the test command requests a parameter change in at least one processor core of the plurality of processor cores; and sending, by the interface unit, control signals to the power state machine coupled to the at least one processor core, wherein the parameter change is forced.
Claim 12
Dependent Claim
25 words
The method of claim 9 , further comprising: receiving, by the interface unit, confirmation from the power state machine that the parameter change is complete.
Claim 13
Dependent Claim
21 words
The method of claim 10 , further comprising: storing the changed parameters in the interface unit in response to the confirmation.
Claim 14
Dependent Claim
19 words
The method of claim 9 , further comprising: storing current parameters of each processor core in the interface unit.
Claim 15
Dependent Claim
33 words
The method of claim 9 , further comprising: sending, by the interface unit, current parameters of the at least one processor core to a test and debug unit responsive to a test command.
Claim 16
Dependent Claim
64 words
The method of claim 9 , further comprising: receiving a test signal from a test and debug unit at a switch unit coupled to the TAP of the at least one processor core; and sending, by the interface unit in response to a test command, control signals to the switch unit to cause the switch unit to apply the test signal to the TAP.
Claim 17
Dependent Claim
32 words
The method of claim 14 , wherein the test signal is one selected from a group consisting of a JTAG test reset signal (TRST) and a JTAG test mode select (TMS) signal.
Claim 18
Independent Claim
96 words
An apparatus comprising: a processor core comprising a processor test access port (TAP), wherein the processor TAP is operable to control testing of the processor core; a power state machine controllably coupled to the processor core to change clock and power parameters of the processor core; and an interface unit controllably coupled to the power state machine, wherein the interface unit comprises an interface TAP operable to receive test commands and the interface unit is operable to force a change to the clock and power parameters responsive to a test command received by the interface TAP.
Claim 19
Independent Claim
96 words
An apparatus comprising: a processor core comprising a processor test access port (TAP), wherein the processor TAP is operable to control testing of the processor core; a power state machine controllably coupled to the processor core to change clock and power parameters of the processor core; and an interface unit controllably coupled to the power state machine, wherein the interface unit comprises an interface TAP operable to receive test commands and the interface unit is operable to force a change to the clock and power parameters responsive to a test command received by the interface TAP.
Claim 20
Dependent Claim
47 words
The apparatus of claim 16 , wherein the interface unit is controllably coupled to the processor TAP to cause a test signal received from a test and debug unit to be applied to the processor TAP in response to a test command received by the interface TAP.
Claim 21
Dependent Claim
32 words
The apparatus of claim 17 , wherein the test signal is one selected from a group consisting of a JTAG test reset signal (TRST) and a JTAG test mode select (TMS) signal.
Claim 22
Independent Claim
85 words
A method for testing a processor core controllably coupled to a power state machine, the method comprising: receiving test commands for testing the processor core at a processor test access port (TAP) comprised in the processor core; receiving test commands to request changes to power and clock parameters of the processor core at an interface TAP of an interface unit controllably coupled to the power state machine; and forcing a change to the parameters in response to a test command received by the interface TAP.
Claim 23
Independent Claim
85 words
A method for testing a processor core controllably coupled to a power state machine, the method comprising: receiving test commands for testing the processor core at a processor test access port (TAP) comprised in the processor core; receiving test commands to request changes to power and clock parameters of the processor core at an interface TAP of an interface unit controllably coupled to the power state machine; and forcing a change to the parameters in response to a test command received by the interface TAP.
Claim 24
Dependent Claim
53 words
The method of claim 19 , further comprising: applying a test signal received from a test and debug unit to the processor TAP in response to a test command received by the interface TAP, wherein the interface unit is controllably coupled to the processor tap to cause the application of the test signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2012-05-18 | 2012-11-17 | 2013-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2016-05-18 | 2016-11-17 | 2017-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2020-05-18 | 2020-11-17 | 2021-05-19 | $7700.00 | Window Closed / Lapsed |