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US7213171B2 Expired / Lapsed US ⏱️ 0.0 years remaining

IEEE 1149.1 tap instruction scan with augmented TLM scan mode

Assignee: Texas Instruments Inc
•
Filing: 2004-02-04
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Granted: 2007-05-01
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Expires: 2024-02-04
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Abstract

Abstract An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Inventors

  • 👤 Baher S. Haroun
  • 👤 Lee D. Whetsel

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 13:45
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536; G01R31/318555; G01R31/318558; G01R31/318563

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 106 words
A process of selecting TAP connections in an integrated circuit having plural cores with each core having a TAP, each TAP is coupled to a TLM, which selects one of the TAPs, and the TAPs and TLM operating in accordance with the IEEE 1149.1 test interface, comprising: A. performing an IEEE 1149.1 instruction scan operation with a TAP instruction augmented with a TLM scan code; B. performing an IEEE 1149.1 data scan operation with TAP selection data to load the TLM with new TAP selection information; and C. performing IEEE 1149.1 instruction and data scan operations on the TAP selected with the new TAP selection information.
Claim 2
Dependent Claim 106 words
A process of selecting TAP connections in an integrated circuit having plural cores with each core having a TAP, each TAP is coupled to a TLM, which selects one of the TAPs, and the TAPs and TLM operating in accordance with the IEEE 1149.1 test interface, comprising: A. performing an IEEE 1149.1 instruction scan operation with a TAP instruction augmented with a TLM scan code; B. performing an IEEE 1149.1 data scan operation with TAP selection data to load the TLM with new TAP selection information; and C. performing IEEE 1149.1 instruction and data scan operations on the TAP selected with the new TAP selection information.
Claim 3
Dependent Claim 43 words
The process of claim 1 in which the performing an IEEE 1149.1 instruction scan operation with a TAP instruction augmented with a TLM scan code includes scanning the TLM scan code through an instruction register of a TAP and then into the TLM.
Claim 4
Dependent Claim 49 words
The process of claim 1 in which the performing an IEEE 1149.1 instruction scan operation with a TAP instruction augmented with a TLM scan code includes scanning the TLM scan code through an instruction register of a TAP and then into an augmentation instruction shift register in the TLM.
Claim 5
Dependent Claim 44 words
The process of claim 1 in which the performing an IEEE 1149.1 instruction scan operation with a TAP instruction augmented with a TAP scan code includes maintaining IEEE 1149.1 instruction and data scan operations on the TAP selected with the new TAP selection information.
Claim 6
Dependent Claim 62 words
The process of claim 1 in which the performing an IEEE 1149.1 instruction scan operation with a TAP instruction augmented with a TLM scan code includes performing an instruction register update, disabling scan access to the currently selected TAP, and enabling the performing an IEEE 1149.1 data scan operation with TAP selection data to load the TLM with new TAP selection information.

References Cited (Backward Citations)

US4698750A Cited
US5737760A Cited
US5689516A Cited
US6073254A Cited
US6142683A Cited
US6134675A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2010-04-30 2010-10-30 2011-05-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2014-04-30 2014-10-30 2015-05-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2018-04-30 2018-10-30 2019-05-01 $7700.00 Window Closed / Lapsed

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