Patent US7339277B2 successfully refreshed from Google Patents.
US7339277B2
Expired / Lapsed
US
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Semiconductor device having passive component and support substrate with electrodes and through electrodes passing through support substrate
Assignee: Fujitsu Ltd
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Filing: 2005-02-16
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Granted: 2008-03-04
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Expires: 2025-02-16
Abstract
Abstract A capacitor comprises a first conducting film 12 formed on a substrate 10 , a first dielectric film 14 formed on the first conducting film, a second conducting film 18 formed on the first dielectric film, a second dielectric film 22 formed above the second conducting film, covering the edge of the second conducting film, a third conducting film 34 formed above the second dielectric film, covering a part of the second dielectric film covering the edge of the second conducting film. The capacitor further comprises an insulation film 28 covering the edge of the second conducing film or the part of the second dielectric film. An effective thickness of the insulation film between the second conducting film and the third conducing film in the region near the edge of the second conducting film can be increased, whereby concentration of electric fields in the region near the edge of the second conducting film. Consequently, the capacitor can have large capacitance without lowering voltage resistance.
Inventors
- 👤 Takeshi Shioga
- 👤 Kazuaki Karasawa
- 👤 Kazuaki Kurihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:32
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/201; H10D84/204; H10D84/212; H10W; H10W20/00; H10W20/40; H10W20/495; H10W20/496; H10W44/00; H10W44/601; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/685; H10W72/00; H10W90/00; H10D1/00; H10D1/60; H10D1/68; H10D1/682; H10W20/20; H10W72/01; H10W72/0198; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/231; H10W72/237; H10W72/241; H10W72/247; H10W72/248; H10W72/851; H10W72/874; H10W72/90; H10W72/931; H10W72/936; H10W72/941; H10W72/9415; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H10W74/15; H10W90/701; H10W90/721; H10W90/724; H10W90/728; H10W90/731; H10W90/738
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
164 words
A semiconductor device comprising: a semiconductor element substrate having first and second sets of contact electrodes; a passive semiconductor substrate mounted to oppose the semiconductor element substrate, the passive semiconductor substrate having opposing upper and lower surfaces, the lower surface of the passive semiconductor substrate facing the semiconductor element substrate; a passive element mounted on the lower surface of the passive semiconductor substrate, between the semiconductor element substrate and the passive semiconductor substrate; passive electrodes electrically connecting the passive element to the first set of contact electrodes of the semiconductor element substrate, the passive electrodes extending through the passive semiconductor substrate to be exposed on the upper surface of the passive semiconductor substrate; and through-electrodes electrically connected to the second set of contact electrodes of the semiconductor element substrate, the through-electrodes extending through the passive element without making electrical contact with the passive element, the through-electrodes extending through the passive semiconductor substrate to be exposed on the upper surface of the passive semiconductor substrate.
Claim 2
Dependent Claim
164 words
A semiconductor device comprising: a semiconductor element substrate having first and second sets of contact electrodes; a passive semiconductor substrate mounted to oppose the semiconductor element substrate, the passive semiconductor substrate having opposing upper and lower surfaces, the lower surface of the passive semiconductor substrate facing the semiconductor element substrate; a passive element mounted on the lower surface of the passive semiconductor substrate, between the semiconductor element substrate and the passive semiconductor substrate; passive electrodes electrically connecting the passive element to the first set of contact electrodes of the semiconductor element substrate, the passive electrodes extending through the passive semiconductor substrate to be exposed on the upper surface of the passive semiconductor substrate; and through-electrodes electrically connected to the second set of contact electrodes of the semiconductor element substrate, the through-electrodes extending through the passive element without making electrical contact with the passive element, the through-electrodes extending through the passive semiconductor substrate to be exposed on the upper surface of the passive semiconductor substrate.
Claim 3
Dependent Claim
26 words
A semiconductor device according to claim 1 , wherein the passive electrodes and the through-electrodes are flip chip-bonded to the electrodes of the semiconductor element substrate.
Claim 4
Dependent Claim
15 words
The semiconductor device according to claim 1 , wherein the passive element is a capacitor.
Claim 5
Dependent Claim
19 words
The semiconductor device according to claim 1 , wherein the passive element is mounted on the semiconductor element substrate.
Claim 6
Dependent Claim
60 words
A semiconductor device according to claim 1 , further comprising: a wiring layer formed on the semiconductor element substrate and having an electric power source line, a ground line, or a signal line, the passive element or the through-electrodes are electrically connected to the semiconductor element substrate via the electric power source line, the ground line, or the signal line.
Claim 7
Dependent Claim
26 words
A semiconductor device according to claim 5 , wherein the passive electrodes and the through-electrodes are flip chip-bonded to the electrodes formed on the wiring layer.
Claim 8
Dependent Claim
156 words
A semiconductor device comprising: a semiconductor element substrate having first and second sets of contact electrodes; a passive substrate mounted to oppose the semiconductor element substrate, the passive substrate having opposing upper and lower surfaces, the lower surface of the passive substrate facing the semiconductor element substrate; a passive element mounted on the lower surface of the passive substrate, between the semiconductor element substrate and the passive substrate; passive electrodes electrically connecting the passive element to the first set of contact electrodes of the semiconductor element substrate, the passive electrodes extending through the passive substrate to be exposed on the upper surface of the passive semiconductor substrate; and through-electrodes electrically connected to the second set of contact electrodes of the semiconductor element substrate, the through-electrodes extending through the passive element without making electrical contact with the passive element, the through-electrodes extending through the passive substrate to be exposed on the upper surface of the passive substrate.
Claim 9
Dependent Claim
156 words
A semiconductor device comprising: a semiconductor element substrate having first and second sets of contact electrodes; a passive substrate mounted to oppose the semiconductor element substrate, the passive substrate having opposing upper and lower surfaces, the lower surface of the passive substrate facing the semiconductor element substrate; a passive element mounted on the lower surface of the passive substrate, between the semiconductor element substrate and the passive substrate; passive electrodes electrically connecting the passive element to the first set of contact electrodes of the semiconductor element substrate, the passive electrodes extending through the passive substrate to be exposed on the upper surface of the passive semiconductor substrate; and through-electrodes electrically connected to the second set of contact electrodes of the semiconductor element substrate, the through-electrodes extending through the passive element without making electrical contact with the passive element, the through-electrodes extending through the passive substrate to be exposed on the upper surface of the passive substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2011-03-04 | 2011-09-03 | 2012-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2015-03-04 | 2015-09-03 | 2016-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2019-03-04 | 2019-09-03 | 2020-03-04 | $7700.00 | Window Closed / Lapsed |