Method of adding on chip capacitors to an integrated circuit

Claim 1

A method of providing a capacitor for an integrated circuit, the integrated circuit having interconnect metallization and an overlying passivation layer comprising a substantially planar surface; the method comprising: opening vias through the passivation layer for contacting the underlying interconnect metallization; filling selected vias with conductive material and selectively depositing a layer of conductive material on the surface of the passivation layer and overlying at least one via of said selected vias to define a bottom electrode of a capacitor and to form an interconnection to the underlying interconnect metallization through the at least one via; providing a capacitor dielectric on the bottom electrode, and providing on the capacitor dielectric a second conductive layer defining a top capacitor electrode, the top capacitor electrode extending laterally of the bottom electrode and overlying at least one other via of said selected vias to form an interconnection to the underlying interconnect metallization through the at least one other via, thereby routing interconnections from each of the electrodes of the capacitor to the interconnect metallization of the underlying integrated circuit through the passivation layer underneath the conductive layers forming the capacitor electrodes.

Claim 2

A method of providing a capacitor for an integrated circuit, the integrated circuit having interconnect metallization and an overlying passivation layer comprising a substantially planar surface; the method comprising: opening vias through the passivation layer for contacting the underlying interconnect metallization; filling selected vias with conductive material and selectively depositing a layer of conductive material on the surface of the passivation layer and overlying at least one via of said selected vias to define a bottom electrode of a capacitor and to form an interconnection to the underlying interconnect metallization through the at least one via; providing a capacitor dielectric on the bottom electrode, and providing on the capacitor dielectric a second conductive layer defining a top capacitor electrode, the top capacitor electrode extending laterally of the bottom electrode and overlying at least one other via of said selected vias to form an interconnection to the underlying interconnect metallization through the at least one other via, thereby routing interconnections from each of the electrodes of the capacitor to the interconnect metallization of the underlying integrated circuit through the passivation layer underneath the conductive layers forming the capacitor electrodes.

Claim 15

A method of adding an on-chip capacitor to an integrated circuit chip comprising a substrate having active devices formed thereon, interconnect metallization and an overlying passivation layer having a planar surface, the method comprising forming capacitors on top of the passivation layer comprising: defining vias through the passivation layer for contacting the interconnect metallization; filling the vias with conductive material and forming a capacitor on the surface of the passivation layer by providing a bottom electrode overlying at least one via of the vias filled with conductive material to form an interconnection from the bottom electrode to the underlying interconnect metallization, providing on the bottom electrode a capacitor dielectric, and providing a top electrode extending over the capacitor dielectric and over at least another via of the vias filled with conductive material to form an interconnection from the top electrode to the underlying interconnect metallization, thereby routing interconnections from each of the electrodes of the capacitor to the interconnect metallization of the underlying integrated circuit through the passivation layer underneath the conductive layers forming the capacitor electrodes.

Claim 16

A method of adding an on-chip capacitor to an integrated circuit chip comprising a substrate having active devices formed thereon, interconnect metallization and an overlying passivation layer having a planar surface, the method comprising forming capacitors on top of the passivation layer comprising: defining vias through the passivation layer for contacting the interconnect metallization; filling the vias with conductive material and forming a capacitor on the surface of the passivation layer by providing a bottom electrode overlying at least one via of the vias filled with conductive material to form an interconnection from the bottom electrode to the underlying interconnect metallization, providing on the bottom electrode a capacitor dielectric, and providing a top electrode extending over the capacitor dielectric and over at least another via of the vias filled with conductive material to form an interconnection from the top electrode to the underlying interconnect metallization, thereby routing interconnections from each of the electrodes of the capacitor to the interconnect metallization of the underlying integrated circuit through the passivation layer underneath the conductive layers forming the capacitor electrodes.

Claim 17

A method of adding capacitors to an integrated circuit chip comprising a substrate having active devices formed thereon, interconnect metallization and an overlying passivation layer having a planar surface with bond pad openings to the underlying metallization; the method comprising: forming capacitors on top of the passivation layer by steps comprising: defining contact openings to the interconnect metallization by opening a plurality of vias through the passivation layer; forming a capacitor on the surface of the passivation layer overlying the plurality of vias by providing a layer of conductive material to form a first electrode contacting the underlying interconnect metallization through one of the plurality of vias, providing a layer of a capacitor dielectric on the first electrode, and providing a second layer of conductive material defining a second electrode extending over the capacitor dielectric and extending laterally of the first electrode, contacting the underlying interconnect metallization through a second via of the plurality of vias thereby routing interconnections from each of the electrodes of the capacitor to the interconnect metallization of the underlying integrated circuit through the passivation layer underneath the conductive layers forming the capacitor.

Claim 18

A method of adding capacitors to an integrated circuit chip comprising a substrate having active devices formed thereon, interconnect metallization and an overlying passivation layer having a planar surface with bond pad openings to the underlying metallization; the method comprising: forming capacitors on top of the passivation layer by steps comprising: defining contact openings to the interconnect metallization by opening a plurality of vias through the passivation layer; forming a capacitor on the surface of the passivation layer overlying the plurality of vias by providing a layer of conductive material to form a first electrode contacting the underlying interconnect metallization through one of the plurality of vias, providing a layer of a capacitor dielectric on the first electrode, and providing a second layer of conductive material defining a second electrode extending over the capacitor dielectric and extending laterally of the first electrode, contacting the underlying interconnect metallization through a second via of the plurality of vias thereby routing interconnections from each of the electrodes of the capacitor to the interconnect metallization of the underlying integrated circuit through the passivation layer underneath the conductive layers forming the capacitor.