Patent US4836909A successfully refreshed from Google Patents.
Patent US7313730B1 successfully refreshed from Google Patents.
US7313730B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Configuration logic for embedded software
Assignee: Nokia Solutions and Networks Oy
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Filing: 2004-05-20
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Granted: 2007-12-25
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Expires: 2024-05-20
Abstract
Abstract An integrated circuit such as an FPGA containing an embedded processor having test circuitry capable of controlling the processor's resources using JTAG commands includes a formatting circuit that formats soft data received from an external storage device into a JTAG-compatible bitstream that can be used by the processor's test circuitry to access and/or control the processor's resources at any time, thereby allowing the embedded processor's resources to be accessed and controlled during FPGA configuration operations before the processor has been initialized to an operational state without using an external configuration tool. For some embodiments, the formatting circuit is a state machine that formats soft data such as firmware code, software programs, processor commands, and the like received from the external storage device into a JTAG-compatible bitstream that can be loaded into and/or used to access the resources of the embedded processor via the processors' test circuitry.
Inventors
- 👤 Peter Ryser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:11
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236
Claims Analysis
Total Claims: 50
Claim 1
Independent Claim
194 words
An integrated circuit (IC), comprising: one or more configurable elements; one or more configuration memory cells to store configuration data for the configurable elements; an embedded processor having one or more resources, a test port to receive a test bitstream, and a debug unit capable of accessing the one or more resources in response to the test bitstream; wherein the test port comprises a JTAG port, and the test bitstream comprises a JTAG-compatible bitstream; a configuration circuit having an input to receive the configuration data from an external storage device, and having an output connected to the configuration memory cells; a formatting circuit having an input to receive soft data from the external storage device and having outputs connected to the processor's test port; a plurality of JTAG input/output (I/O) pins; a JTAG-compliant test circuit having a plurality of inputs coupled to corresponding JTAG I/O pins, and having a plurality of outputs; and a select circuit having first inputs coupled to corresponding outputs of the JTAG-compliant test circuit, second inputs coupled to corresponding outputs of the formatting circuit, outputs coupled to the processor's JTAG port, and a control terminal to receive a mode signal.
Claim 2
Dependent Claim
194 words
An integrated circuit (IC), comprising: one or more configurable elements; one or more configuration memory cells to store configuration data for the configurable elements; an embedded processor having one or more resources, a test port to receive a test bitstream, and a debug unit capable of accessing the one or more resources in response to the test bitstream; wherein the test port comprises a JTAG port, and the test bitstream comprises a JTAG-compatible bitstream; a configuration circuit having an input to receive the configuration data from an external storage device, and having an output connected to the configuration memory cells; a formatting circuit having an input to receive soft data from the external storage device and having outputs connected to the processor's test port; a plurality of JTAG input/output (I/O) pins; a JTAG-compliant test circuit having a plurality of inputs coupled to corresponding JTAG I/O pins, and having a plurality of outputs; and a select circuit having first inputs coupled to corresponding outputs of the JTAG-compliant test circuit, second inputs coupled to corresponding outputs of the formatting circuit, outputs coupled to the processor's JTAG port, and a control terminal to receive a mode signal.
Claim 3
Dependent Claim
18 words
The IC of claim 1 , wherein the formatting circuit formats the soft data into the test bitstream.
Claim 4
Dependent Claim
37 words
The IC of claim 1 , further comprising: test circuitry having an input port coupled to one or more corresponding test pins of the IC and having an output port selectively coupled to the processor's test port.
Claim 5
Dependent Claim
30 words
The IC of claim 1 , wherein the formatting circuit further comprises a control input to receive an enable signal for enabling the formatting circuit to process the soft data.
Claim 6
Dependent Claim
25 words
The IC of claim 4 , wherein de-assertion of the enable signal prevents the formatting circuit from processing data received from the external storage device.
Claim 7
Dependent Claim
22 words
The IC of claim 1 , wherein the soft data comprises information for controlling the one or more resources of the processor.
Claim 8
Dependent Claim
16 words
The IC of claim 6 , wherein the test bitstream comprises bus commands for the processor.
Claim 9
Dependent Claim
23 words
The IC of claim 1 , wherein the test bitstream comprises firmware code to be loaded into a cache memory of the processor.
Claim 10
Dependent Claim
22 words
The IC of claim 1 , wherein the test bitstream comprises data to be loaded into an architectural register of the processor.
Claim 11
Dependent Claim
13 words
The IC of claim 1 , wherein the soft data comprises firmware code.
Claim 12
Dependent Claim
16 words
The IC of claim 10 , wherein the one or more resources comprises a cache memory.
Claim 13
Dependent Claim
42 words
The IC of claim 1 , wherein the soft data is stored in the external storage device as a plurality of bit pairs, each bit pair comprising a JTAG-compatible test data input (TDI) bit and a JTAG-compatible test mode select (TMS) bit.
Claim 14
Dependent Claim
31 words
The IC of claim 12 , wherein the soft data includes a start code that instructs the formatting circuit to format subsequent portions of the soft data into the JTAG-compatible bitstream.
Claim 15
Dependent Claim
29 words
The IC of claim 12 , wherein the external storage device comprises: a first partition for storing the configuration data; and a second partition for storing the soft data.
Claim 16
Dependent Claim
27 words
The IC of claim 12 , wherein the formatting circuit is configurable to receive the bit pairs from the external storage device either serially or in parallel.
Claim 17
Dependent Claim
52 words
The IC of claim 1 , wherein the select circuit forwards the JTAG-compatible bitstream from the formatting circuit to the processor's JTAG port when the mode signal is in a first state, and connects the JTAG-compliant test circuit to the processor's JTAG port when the mode signal is in a second state.
Claim 18
Dependent Claim
49 words
The IC of claim 1 , wherein the formatting circuit comprises: one or more first formatting circuits configured to receive the soft data serially from the external storage device; and one or more second formatting circuits configured to receive the soft data in parallel from the external storage device.
Claim 19
Dependent Claim
27 words
The IC of claim 1 , wherein the formatting circuit is configurable to receive the soft data from the external storage device either serially or in parallel.
Claim 20
Dependent Claim
181 words
An integrated circuit (IC), comprising: a plurality of configurable elements; an embedded processor having one or more resources, a test port to receive a test bitstream, and means for accessing the one or more resources; wherein the test port comprises a JTAG port, and the test bitstream comprises a JTAG-compatible bitstream; one or more configuration pins to receive data from an external storage device during configuration of the IC, the data including configuration data for configuring the configurable elements and soft data for use by the processor; means for formatting the soft data received from the external storage device via the one or more configuration pins to generate the test bitstream; plurality of JTAG input/output (I/O) pins; a JTAG-compliant test circuit having a plurality of inputs coupled to corresponding JTAG I/O pins, and having a plurality of outputs; and a select circuit having first inputs coupled to corresponding outputs of the JTAG-compliant test circuit, second inputs coupled to corresponding outputs of the means for formatting, outputs coupled to the processor's JTAG port, and a control terminal to receive a mode signal.
Claim 21
Dependent Claim
181 words
An integrated circuit (IC), comprising: a plurality of configurable elements; an embedded processor having one or more resources, a test port to receive a test bitstream, and means for accessing the one or more resources; wherein the test port comprises a JTAG port, and the test bitstream comprises a JTAG-compatible bitstream; one or more configuration pins to receive data from an external storage device during configuration of the IC, the data including configuration data for configuring the configurable elements and soft data for use by the processor; means for formatting the soft data received from the external storage device via the one or more configuration pins to generate the test bitstream; plurality of JTAG input/output (I/O) pins; a JTAG-compliant test circuit having a plurality of inputs coupled to corresponding JTAG I/O pins, and having a plurality of outputs; and a select circuit having first inputs coupled to corresponding outputs of the JTAG-compliant test circuit, second inputs coupled to corresponding outputs of the means for formatting, outputs coupled to the processor's JTAG port, and a control terminal to receive a mode signal.
Claim 22
Dependent Claim
37 words
The IC of claim 19 , further comprising: test circuitry having an input port coupled to one or more corresponding test pins of the IC and having an output port selectively coupled to the processor's test port.
Claim 23
Dependent Claim
26 words
The IC of claim 19 , wherein the one or more resources comprise a cache memory and the soft data comprises firmware code for the processor.
Claim 24
Dependent Claim
24 words
The IC of claim 19 , wherein the one or more resources comprise a bus system and the soft data comprises a bus command.
Claim 25
Dependent Claim
28 words
The IC of claim 19 , wherein the means for formatting is configurable to receive the soft data from the external storage device either serially or in parallel.
Claim 26
Dependent Claim
42 words
The IC of claim 19 , wherein the soft data is stored in the external storage device as a plurality of bit pairs, each bit pair comprising a JTAG-compatible test data input (TDI) bit and a JTAG-compatible test mode select (TMS) bit.
Claim 27
Dependent Claim
32 words
The IC of claim 24 , wherein the soft data includes a start code that instructs the means for formatting to format subsequent portions of the soft data into the JTAG-compatible bitstream.
Claim 28
Dependent Claim
29 words
The IC of claim 19 , wherein the external storage device comprises: a first partition for storing the configuration data; and a second partition for storing the soft data.
Claim 29
Dependent Claim
18 words
The IC of claim 19 , further comprising: means for configuring the configurable elements with the configuration data.
Claim 30
Dependent Claim
52 words
The IC of claim 19 , wherein the select circuit forwards the JTAG-compatible bitstream from the formatting circuit to the processor's JTAG port when the mode signal is in a first state, and connects the JTAG-compliant test circuit to the processor's JTAG port when the mode signal is in a second state.
Claim 31
Independent Claim
143 words
A method of controlling one or more resources of a processor embedded in an integrated circuit (IC), the processor including a test port and test circuitry, comprising: loading soft data from an external storage device into the IC via one or more configuration pins on the IC; formatting the soft data into a test bitstream and associated test control signals; forwarding the test bitstream and the associated test control signals to the processor via a select circuit coupled to receive the test bitstream and the associated test control signals as a first input and coupled to receive outputs of a JTAG-compliant test circuit as a second input; loading the test bitstream and the associated test control signals into the processor via the test port; and implementing one or more functions in the processor as specified by the test bitstream via the test circuitry.
Claim 32
Independent Claim
143 words
A method of controlling one or more resources of a processor embedded in an integrated circuit (IC), the processor including a test port and test circuitry, comprising: loading soft data from an external storage device into the IC via one or more configuration pins on the IC; formatting the soft data into a test bitstream and associated test control signals; forwarding the test bitstream and the associated test control signals to the processor via a select circuit coupled to receive the test bitstream and the associated test control signals as a first input and coupled to receive outputs of a JTAG-compliant test circuit as a second input; loading the test bitstream and the associated test control signals into the processor via the test port; and implementing one or more functions in the processor as specified by the test bitstream via the test circuitry.
Claim 33
Dependent Claim
22 words
The method of claim 29 , wherein the test port comprises a JTAG port and the test bitstream comprises a JTAG-compliant bitstream.
Claim 34
Dependent Claim
29 words
The method of claim 29 , wherein implementing one or more functions comprises loading firmware code stored in the external storage device into a cache memory within the processor.
Claim 35
Dependent Claim
32 words
The method of claim 29 , wherein implementing one or more functions comprises updating data stored in a memory element within the processor with soft data retrieved from the external storage device.
Claim 36
Dependent Claim
36 words
The method of claim 29 , wherein implementing one or more functions comprises providing instructions received from the external storage device to the processor to initialize one or more of the resources to a desired state.
Claim 37
Dependent Claim
33 words
The method of claim 30 , further comprising: storing the soft data in the external storage device as a plurality of JTAG test data input (TDI) and test mode select (TMS) bit pairs.
Claim 38
Dependent Claim
29 words
The method of claim 34 , further comprising: inserting a start code as an initial set of bit pairs of the soft data stored in the external storage device.
Claim 39
Dependent Claim
19 words
The method of claim 35 , further comprising: enabling the formatting in response to detection of the start code.
Claim 40
Dependent Claim
43 words
The method of claim 29 , further comprising: storing configuration data for one or more configurable elements of the IC in a first partition of the external storage device; and storing the soft data in a second partition of the external storage device.
Claim 41
Dependent Claim
26 words
The method of claim 37 , further comprising: loading the configuration data into a configuration memory associated with one or more configurable elements of the IC.
Claim 42
Independent Claim
186 words
A method of configuring an integrated circuit (IC) having an embedded processor that includes test circuitry, comprising: storing configuration data capable of configuring one or more configurable elements of the IC in an external storage device; storing soft data capable of accessing one or more resources of the embedded processor into the external storage device; loading the configuration data from the external storage device into a configuration memory of the IC via one or more IC configuration pins; loading the soft data from the external storage device into the IC via the one or more IC configuration pins; formatting the soft data into a test bitstream and associated test control signals; forwarding the test bitstream and the associated test control signals to the processor via a select circuit coupled to receive the test bitstream and the associated test control signals as a first input and coupled to receive outputs of a JTAG-compliant test circuit as a second input; and loading the data embodied in the test bitstream into one or more resources selected by the processor's test circuitry in response to the associated test control signals.
Claim 43
Independent Claim
186 words
A method of configuring an integrated circuit (IC) having an embedded processor that includes test circuitry, comprising: storing configuration data capable of configuring one or more configurable elements of the IC in an external storage device; storing soft data capable of accessing one or more resources of the embedded processor into the external storage device; loading the configuration data from the external storage device into a configuration memory of the IC via one or more IC configuration pins; loading the soft data from the external storage device into the IC via the one or more IC configuration pins; formatting the soft data into a test bitstream and associated test control signals; forwarding the test bitstream and the associated test control signals to the processor via a select circuit coupled to receive the test bitstream and the associated test control signals as a first input and coupled to receive outputs of a JTAG-compliant test circuit as a second input; and loading the data embodied in the test bitstream into one or more resources selected by the processor's test circuitry in response to the associated test control signals.
Claim 44
Dependent Claim
28 words
The method of claim 39 , wherein the soft data comprises firmware code for the processor and one of the resources comprises a cache memory of the processor.
Claim 45
Dependent Claim
18 words
The method of claim 39 , wherein one of the resources comprises an architectural register of the processor.
Claim 46
Dependent Claim
14 words
The method of claim 39 , wherein the test bitstream comprises a JTAG-compliant bitstream.
Claim 47
Dependent Claim
17 words
The method of claim 42 , further comprising: disabling a JTAG-compliant test architecture associated with the IC.
Claim 48
Dependent Claim
28 words
The method of claim 42 , further comprising: storing the soft data in the external storage device as a plurality of JTAG data and mode select bit pairs.
Claim 49
Dependent Claim
20 words
The method of claim 44 , wherein the soft data further comprises a start code capable of enabling the formatting.
Claim 50
Dependent Claim
35 words
The method of claim 39 , further comprising: storing the configuration data in a first partition of the external storage device and storing the soft data in a second partition of the external storage device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-12-24 | 2011-06-25 | 2011-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-12-24 | 2015-06-25 | 2015-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-12-24 | 2019-06-25 | 2019-12-25 | $7700.00 | Window Closed / Lapsed |