US6983441B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Embedding a JTAG host controller into an FPGA design
Assignee: Texas Instruments Inc
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Filing: 2002-06-28
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Granted: 2006-01-03
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Expires: 2022-06-28
Abstract
Abstract A method for embedding a Joint Test Action Group (JTAG) standard IEEE 1149.1 host controller into a field programmable gate array (FPGA) for platform development and DSP programming, and boundary scan of targeted hardware using JTAG commands and architecture is described. The FPGA-based JTAG host controller is bussed directly into the FPGA core, bypassing the board's JTAG communication port.
Inventors
- 👤 Douglas Albert Wescott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:11
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/48; G11C2029/0401; G11C29/12; G11C29/18; G11C29/30; G11C2029/3202
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
117 words
A system for configuring a field programmable gate array (FPGA) as a peripheral Joint Test Access Group (JTAG) host controller for a peripheral hardware target, comprising: a processor that includes source code for a JTAG host controller; an FPGA attached to a peripheral printed circuit board, the FPGA including: a memory array that is programmed with the source code for the JTAG host controller, by the external processor; a processor core; and JTAG interface logic; a serial connector that connects the processor to the FPGA; and a hardware target that is JTAG-compliant and attached to the peripheral printed circuit board; wherein the FPGA sends JTAG host controller signals through the JTAG interface logic to the hardware target.
Claim 2
Independent Claim
117 words
A system for configuring a field programmable gate array (FPGA) as a peripheral Joint Test Access Group (JTAG) host controller for a peripheral hardware target, comprising: a processor that includes source code for a JTAG host controller; an FPGA attached to a peripheral printed circuit board, the FPGA including: a memory array that is programmed with the source code for the JTAG host controller, by the external processor; a processor core; and JTAG interface logic; a serial connector that connects the processor to the FPGA; and a hardware target that is JTAG-compliant and attached to the peripheral printed circuit board; wherein the FPGA sends JTAG host controller signals through the JTAG interface logic to the hardware target.
Claim 3
Dependent Claim
34 words
The system of claim 1 , wherein the memory array includes at least one of a random access memory, a read only memory, an erasable programmable read only memory, and a first-in first-out buffer.
Claim 4
Dependent Claim
16 words
The system of claim 1 , wherein the FPGA is removable from the printed circuit board.
Claim 5
Dependent Claim
26 words
The system of claim 1 , wherein the hardware target includes one of a digital signal processor, an application specific integrated circuit, and an integrated circuit.
Claim 6
Dependent Claim
34 words
The system of claim 1 , wherein JTAG host controller signals are sent from the FPGA to the target hardware without use of a controller that is external to the peripheral printed circuit board.
Claim 7
Dependent Claim
27 words
The system of claim 1 , wherein the serial connector comprises one of a Universal Serial Bus (USB) connector, a Firewall (1394) connector, and an Ethernet connector.
Claim 8
Independent Claim
95 words
A method for configuring a field programmable gate array (FPGA) as a peripheral Joint Test Access Group (JTAG) host controller for a peripheral hardware target, comprising: programming the FPGA on a peripheral printed circuit board to include: a memory array; a processor core; and JTAG interface logic; loading the memory array of the FPGA with source code of a JTAG host controller from an external processor through a serial connector; and communicating JTAG signals through the JTAG interface logic to the hardware target that is JTAG-compliant and is located on the peripheral printed circuit board.
Claim 9
Independent Claim
95 words
A method for configuring a field programmable gate array (FPGA) as a peripheral Joint Test Access Group (JTAG) host controller for a peripheral hardware target, comprising: programming the FPGA on a peripheral printed circuit board to include: a memory array; a processor core; and JTAG interface logic; loading the memory array of the FPGA with source code of a JTAG host controller from an external processor through a serial connector; and communicating JTAG signals through the JTAG interface logic to the hardware target that is JTAG-compliant and is located on the peripheral printed circuit board.
Claim 10
Dependent Claim
32 words
The method of claim 7 , wherein the memory array includes one of a random access memory, a read only memory, an erasable programmable read only memory, and a first-in first-out buffer.
Claim 11
Dependent Claim
29 words
The method of claim 7 , wherein the memory array includes buffers for buffering data sent to the hardware target and for buffering data received from the external processor.
Claim 12
Dependent Claim
26 words
The method of claim 7 , wherein the target hardware comprises one of a digital signal processor, an application specific integrated circuit, and an integrated circuit.
Claim 13
Dependent Claim
32 words
The method of claim 7 , wherein JTAG signals are sent by the FPGA to the hardware target without use of a controller that is external to the peripheral printed circuit board.
Claim 14
Dependent Claim
27 words
The method of claim 7 , wherein the serial connector comprises one of a Universal Serial Bus (USB) connector, a Firewall (1394) connector, and an Ethernet connector.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-01-02 | 2009-07-04 | 2010-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-01-02 | 2013-07-04 | 2014-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-01-02 | 2017-07-04 | 2018-01-03 | $7700.00 | Window Closed / Lapsed |