US6137738A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for in-system programming of serially configured EEPROMS using a JTAG interface of a field programmable gate array
Assignee: Lattice Semiconductor Corp
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Filing: 1999-11-30
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Granted: 2000-10-24
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Expires: 2019-11-30
Abstract
Abstract A method for programming an electrically erasable programmable read only memory (EEPROM) while mounted on a printed circuit board. The EEPROM is used as a memory storage device for a field programmable gate array (FPGA), which is mounted on the printed circuit board. The board and FPGA have a joint test action group (JTAG) test interface. The FPGA contains a test access port (TAP) and user defined internal scan registers. The method includes providing a connection between the TAP of the FPGA and the EEPROM. Data is provided to the internal scan data registers of the FPGA via the JTAG test interface. Data is transferred via the internal scan data registers to the EEPROM without interrupting operation of the FPGA.
Inventors
- 👤 James Joseph Vorgert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:34
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/48; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/102; G11C2216/00; G11C2216/12; G11C2216/30
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
101 words
A method for inputting data in a data storage device adapted to be mounted to a printed circuit board, the board having an interface, the storage device used as a memory storage device for an integrated circuit mounted on the printed circuit board, the integrated circuit having internal scan data registers and an access port, the method comprising: providing a connection between the access port of the integrated circuit and the storage device; providing data to the internal scan data registers of the integrated circuit via the interface; and transferring data via the internal scan data registers to the storage device.
Claim 2
Independent Claim
101 words
A method for inputting data in a data storage device adapted to be mounted to a printed circuit board, the board having an interface, the storage device used as a memory storage device for an integrated circuit mounted on the printed circuit board, the integrated circuit having internal scan data registers and an access port, the method comprising: providing a connection between the access port of the integrated circuit and the storage device; providing data to the internal scan data registers of the integrated circuit via the interface; and transferring data via the internal scan data registers to the storage device.
Claim 3
Dependent Claim
31 words
The method of claim 1 wherein the interface comprises ajoint test access group (JTAG) test interface and provides test data input, test mode select, test clock, and test data output signals.
Claim 4
Dependent Claim
15 words
The method of claim 1 wherein the access port comprises a test access port (TAP).
Claim 5
Dependent Claim
18 words
The method of claim 1 wherein the storage device comprises an electrically erasable programmable read only memory (EEPROM).
Claim 6
Dependent Claim
16 words
The method of claim 1 wherein the integrated circuit comprises a field programmable gate array (FPGA).
Claim 7
Independent Claim
100 words
A method for inputting data in a data storage device while mounted on a printed circuit board, the board having a test interface, the storage device used as a memory storage device for a programmable gate array (FPGA), mounted on the printed circuit board, the FPGA having internal scan data registers and an access port, the method comprising: providing a connection between the access port of the FPGA and the storage device; providing data to the internal scan data registers of the FPGA via the test interface; and transferring data via the internal scan data registers to the storage device.
Claim 8
Independent Claim
100 words
A method for inputting data in a data storage device while mounted on a printed circuit board, the board having a test interface, the storage device used as a memory storage device for a programmable gate array (FPGA), mounted on the printed circuit board, the FPGA having internal scan data registers and an access port, the method comprising: providing a connection between the access port of the FPGA and the storage device; providing data to the internal scan data registers of the FPGA via the test interface; and transferring data via the internal scan data registers to the storage device.
Claim 9
Dependent Claim
33 words
The method of claim 6 wherein the test interface comprises a joint test access group (JTAG) test interface and provides test data input, test mode select, test clock, and test data output signals.
Claim 10
Dependent Claim
15 words
The method of claim 6 wherein the access port comprises a test access port (TAP).
Claim 11
Dependent Claim
17 words
The method of claim 6 wherein the storage device comprises an electrically erasable programmable read only memory.
Claim 12
Independent Claim
106 words
A method for programming a data storage device while mounted on a printed circuit board, the board having a joint test access group (JTAG) test interface, the storage device used as a memory storage device for a field programmable gate array (FPGA), mounted on the printed circuit board, the FPGA having internal scan data registers and a test access port (TAP), the method comprising: providing a connection between the TAP of the FPGA and the storage device; providing data to the internal scan data registers of the FPGA via the JTAG test interface; and transferring data via the internal scan data registers to the storage device.
Claim 13
Independent Claim
106 words
A method for programming a data storage device while mounted on a printed circuit board, the board having a joint test access group (JTAG) test interface, the storage device used as a memory storage device for a field programmable gate array (FPGA), mounted on the printed circuit board, the FPGA having internal scan data registers and a test access port (TAP), the method comprising: providing a connection between the TAP of the FPGA and the storage device; providing data to the internal scan data registers of the FPGA via the JTAG test interface; and transferring data via the internal scan data registers to the storage device.
Claim 14
Dependent Claim
24 words
The method of claim 10 wherein the JTAG test interface provides test data input, test mode select, test clock, and test data output signals.
Claim 15
Dependent Claim
18 words
The method of claim 10 wherein the data storage device comprises an electrically erasable programmable read only memory.
Claim 16
Dependent Claim
18 words
The method of claim 10 wherein data is transferred to the storage device without interruption of FPGA operation.
Claim 17
Independent Claim
113 words
A method for programming an electrically erasable programmable read only memory (EEPROM) while mounted on a printed circuit board, the board having a joint test access group (JTAG) test interface, the EEPROM used as a memory storage device for a field programmable gate array (FPGA), mounted on the printed circuit board, the FPGA having internal scan data registers and a test access port (TAP), the method comprising: providing a connection between the TAP of the FPGA and the EEPROM; providing data to the internal scan data registers of the FPGA via the JTAG test interface; and transferring data via the internal scan data registers to the EEPROM without interrupting operation of the FPGA.
Claim 18
Independent Claim
113 words
A method for programming an electrically erasable programmable read only memory (EEPROM) while mounted on a printed circuit board, the board having a joint test access group (JTAG) test interface, the EEPROM used as a memory storage device for a field programmable gate array (FPGA), mounted on the printed circuit board, the FPGA having internal scan data registers and a test access port (TAP), the method comprising: providing a connection between the TAP of the FPGA and the EEPROM; providing data to the internal scan data registers of the FPGA via the JTAG test interface; and transferring data via the internal scan data registers to the EEPROM without interrupting operation of the FPGA.
Claim 19
Dependent Claim
24 words
The method of claim 14 wherein the JTAG test interface provides test data input, test mode select, test clock, and test data output signals.
Claim 20
Dependent Claim
95 words
A circuit comprising: a data storage device adapted to be mounted to a printed circuit board; said printed circuit board having a joint test access group (JTAG) test interface a field programmable gate array (FPGA), adapted to be mounting on said printed circuit board, said FPGA having internal scan data registers and a test access port (TAP); circuitry connecting said data registers to said storage device; and circuitry connecting said data registers to said JTAG test interface via said TAP such that data is transferable via said internal scan data registers to said storage device.
Claim 21
Dependent Claim
95 words
A circuit comprising: a data storage device adapted to be mounted to a printed circuit board; said printed circuit board having a joint test access group (JTAG) test interface a field programmable gate array (FPGA), adapted to be mounting on said printed circuit board, said FPGA having internal scan data registers and a test access port (TAP); circuitry connecting said data registers to said storage device; and circuitry connecting said data registers to said JTAG test interface via said TAP such that data is transferable via said internal scan data registers to said storage device.
Claim 22
Dependent Claim
24 words
The circuit of claim 16 wherein said JTAG test interface provides test data input, test mode select, test clock, and test data output signals.
Claim 23
Dependent Claim
19 words
The circuit of claim 16 wherein said data storage device comprises an electrically erasable programmable read only memory (EEPROM).
Claim 24
Dependent Claim
18 words
The circuit of claim 16 wherein data is transferred to the storage device without interruption of FPGA operation.
References Cited (Backward Citations)
US5270977A
Cited
US5471430A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-24 | 2004-04-24 | 2004-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-24 | 2008-04-24 | 2008-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-24 | 2012-04-24 | 2012-10-24 | $7700.00 | Window Closed / Lapsed |