Patent US7248532B2 successfully refreshed from Google Patents.
US7248532B2
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Device, system and method for reducing power in a memory device during standby modes
Assignee: Round Rock Research LLC
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Filing: 2005-02-14
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Granted: 2007-07-24
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Expires: 2025-02-14
Abstract
Abstract A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and second reference signals. The circuit also includes a switching device for switching between the first and second reference signals in response to the standby mode command and further controls an internal operational power regulator to adjust between normal and low-power outputs for further reducing the power to portions of the memory device.
Inventors
- 👤 Aaron M. Schoenfeld
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/40615; G11C11/4063; G11C11/407; G11C11/4074; G11C5/00; G11C5/14; G11C2207/00; G11C2207/22; G11C2207/2227; G11C2211/00; G11C2211/401; G11C2211/406; G11C2211/4067; G11C7/00; G11C7/10; G11C7/1015; G11C7/1045
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
117 words
A method for generating power on at least a portion of a memory device, comprising: switching between a plurality of reference signals corresponding to a plurality of memory device power modes, wherein switching includes switching from one of the plurality of reference signals corresponding to an operational one of the plurality of memory device power modes to one of the plurality of reference signals corresponding to a reduced power mode when the memory device is engaged space in space a self-refresh one of the plurality of memory device power modes; and regulating the power on the memory device to one of a plurality of voltages in response to a selected one of the plurality of reference signals.
Claim 2
Independent Claim
117 words
A method for generating power on at least a portion of a memory device, comprising: switching between a plurality of reference signals corresponding to a plurality of memory device power modes, wherein switching includes switching from one of the plurality of reference signals corresponding to an operational one of the plurality of memory device power modes to one of the plurality of reference signals corresponding to a reduced power mode when the memory device is engaged space in space a self-refresh one of the plurality of memory device power modes; and regulating the power on the memory device to one of a plurality of voltages in response to a selected one of the plurality of reference signals.
Claim 3
Independent Claim
103 words
A method for generating power on at least a portion of a memory device, comprising: switching between a plurality of reference signals corresponding to a plurality of memory device power modes; regulating on the memory device the power on the memory device to one of a plurality of voltages in response to a selected one of the plurality of reference signals; and routing a portion of the power to a first portion of the memory device and retaining operational power to a second portion of the memory device during a self-refresh of one of the at least one portion of the memory device.
Claim 4
Independent Claim
103 words
A method for generating power on at least a portion of a memory device, comprising: switching between a plurality of reference signals corresponding to a plurality of memory device power modes; regulating on the memory device the power on the memory device to one of a plurality of voltages in response to a selected one of the plurality of reference signals; and routing a portion of the power to a first portion of the memory device and retaining operational power to a second portion of the memory device during a self-refresh of one of the at least one portion of the memory device.
Claim 5
Dependent Claim
144 words
A circuit for adjusting power during a plurality of modes of a memory device, comprising: a plurality of reference signals corresponding to the plurality of modes, wherein one of the plurality of modes includes one of a standby mode during a self-refresh of memory cells within the memory device; a switching device coupled to the plurality of reference signals at a corresponding plurality of inputs, the switching device further responsive to power reduction control signals configured to select at control inputs one of the plurality of reference signals on an output during a corresponding one of the plurality of modes; and a regulator coupled and responsive to the output of the switching device, the regulator configured to output an operational power of one of a plurality of voltages corresponding to the one of the plurality of modes as regulated from an external operational power.
Claim 6
Dependent Claim
144 words
A circuit for adjusting power during a plurality of modes of a memory device, comprising: a plurality of reference signals corresponding to the plurality of modes, wherein one of the plurality of modes includes one of a standby mode during a self-refresh of memory cells within the memory device; a switching device coupled to the plurality of reference signals at a corresponding plurality of inputs, the switching device further responsive to power reduction control signals configured to select at control inputs one of the plurality of reference signals on an output during a corresponding one of the plurality of modes; and a regulator coupled and responsive to the output of the switching device, the regulator configured to output an operational power of one of a plurality of voltages corresponding to the one of the plurality of modes as regulated from an external operational power.
Claim 7
Dependent Claim
18 words
The circuit of claim 3 , wherein the plurality of reference signals are generated from a voltage divider.
Claim 8
Dependent Claim
30 words
The circuit of claim 3 , wherein the switching device comprises a multiplexer including the plurality of inputs, the output and control inputs responsive to the power reduction control signals.
Claim 9
Dependent Claim
25 words
The circuit of claim 3 , wherein one of the plurality of modes further includes a power-down mode of memory cells within the memory device.
Claim 10
Independent Claim
80 words
A method of reducing power consumed on a memory device, comprising: powering a first portion of the memory device with a reduced operational power as regulated on the memory device to one of a plurality of voltages in response to a selected one of a plurality of reference signals, wherein powering the first portion includes regulating to the reduced operational power in response to a self-refresh command; and powering a second portion of the memory device with full operational power.
Claim 11
Independent Claim
80 words
A method of reducing power consumed on a memory device, comprising: powering a first portion of the memory device with a reduced operational power as regulated on the memory device to one of a plurality of voltages in response to a selected one of a plurality of reference signals, wherein powering the first portion includes regulating to the reduced operational power in response to a self-refresh command; and powering a second portion of the memory device with full operational power.
Claim 12
Independent Claim
81 words
A method of reducing power consumed on a memory device, comprising: powering a first portion of the memory device with a reduced operational power as regulated on the memory device to one of a plurality of voltages in response to a selected one of a plurality of reference signals, wherein powering the first portion includes regulating to the full operational power in response to a memory access command; and powering a second portion of the memory device with full operational power.
Claim 13
Independent Claim
81 words
A method of reducing power consumed on a memory device, comprising: powering a first portion of the memory device with a reduced operational power as regulated on the memory device to one of a plurality of voltages in response to a selected one of a plurality of reference signals, wherein powering the first portion includes regulating to the full operational power in response to a memory access command; and powering a second portion of the memory device with full operational power.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-07-23 | 2011-01-22 | 2011-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-07-23 | 2015-01-22 | 2015-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-07-23 | 2019-01-22 | 2019-07-24 | $7700.00 | Window Closed / Lapsed |