US6563746B2
Expired / Lapsed
US
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Circuit for entering/exiting semiconductor memory device into/from low power consumption mode and method of controlling internal circuit at low power consumption mode
Assignee: Socionext Inc
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Filing: 2001-03-30
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Granted: 2003-05-13
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Expires: 2021-03-30
Abstract
Abstract An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
Inventors
- 👤 Shinya Fujioka
- 👤 Tomohiro Kawakubo
- 👤 Koichi Nishimura
- 👤 Kotoku Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:15
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/325; G06F1/3268; G06F1/3275; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/40615; G11C14/00; G11C5/00; G11C5/14; G11C5/145; G11C5/147; H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; G11C2207/00; G11C2207/22; G11C2207/2227; G11C2211/00; G11C2211/401; G11C2211/406; G11C2211/4067; Y; Y02; Y02D; Y02D10/00; Y02D30/00; Y02D30/50
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
71 words
A semiconductor memory device comprising: an internal voltage generator 22 receiving a power supply voltage from an exterior for generating an internal voltage to be supplied to an internal circuit; and an entry circuit for inactivating said internal voltage generator in response to one or more control signals received from the exterior and entering the device into a low power consumption mode in which the generation of said internal voltage stops.
Claim 2
Dependent Claim
71 words
A semiconductor memory device comprising: an internal voltage generator 22 receiving a power supply voltage from an exterior for generating an internal voltage to be supplied to an internal circuit; and an entry circuit for inactivating said internal voltage generator in response to one or more control signals received from the exterior and entering the device into a low power consumption mode in which the generation of said internal voltage stops.
Claim 3
Dependent Claim
39 words
The semiconductor memory device according to claim 1 , further comprising a word line connected with memory cells, and wherein said internal voltage generator includes a booster for generating a boost voltage to be supplied to said word line.
Claim 4
Dependent Claim
30 words
The semiconductor memory device according to claim 1 , wherein said internal voltage generator includes a substrate voltage generator for generating a substrate voltage to be supplied to a substrate.
Claim 5
Dependent Claim
51 words
The A semiconductor memory device according to claim 1 , further comprising a memory core having a plurality of memory cells, and wherein said internal voltage generator includes an internal supply voltage generator for generating an internal supply voltage to be supplied to said memory core lower than said supply voltage.
Claim 6
Dependent Claim
49 words
The semiconductor memory device according to claim 1 , further comprising a memory core including memory cells and a bit line connected with the memory cells, and wherein said internal voltage generator includes a precharging voltage generator for generating a precharging voltage to be supplied to said bit line.
Claim 7
Dependent Claim
36 words
The semiconductor memory device according to claim 1 , further comprising an external voltage supplying circuit for supplying said power supply voltage as said internal voltage to said internal circuit during said low power consumption mode.
Claim 8
Dependent Claim
48 words
The semiconductor memory device according to claim 1 , wherein said entry circuit receives a reset signal as said one or more control signals, and enters the device into said low power consumption mode, said reset signal being a signal for inactivating said internal circuit from the exterior.
Claim 9
Dependent Claim
51 words
The semiconductor memory device according to claim 1 , wherein said entry circuit receives said one or more control signals from the exterior, and enters the device into said low power consumption mode when one or more levels of the one or more control signals indicate a low power consumption command.
Claim 10
Dependent Claim
103 words
The semiconductor memory device according to claim 8 , wherein said entry circuit receives from the exterior a reset signal as a first control signal of said one or more control signals and a chip enable signal as a second control signal of said one or more control signals, and enters the device into said low power consumption mode when the levels of the reset signal and the chip enable signal indicate said low power consumption command, said reset signal inactivating said internal circuit and said chip enable signal activating a part of said internal circuit to be operated in a read/write operation.
Claim 11
Dependent Claim
44 words
The semiconductor memory device according to claim 9 , wherein said entry circuit enters the device into said low power consumption mode when said reset signal is inactivated during a predetermined period and then said chip enable signal is activated during a predetermined period.
Claim 12
Dependent Claim
48 words
The semiconductor memory device according to claim 8 , wherein said entry circuit receives said control signals during said low power consumption mode and exits the device from the low power consumption mode when the levels of said control signals indicate exit of the low power consumption mode.
Claim 13
Dependent Claim
52 words
The semiconductor memory device according to claim 1 , wherein: said one or more control signals include a low power consumption mode signal; and said entry circuit receives the predetermined level or the transition edge of said low power consumption mode signal and enters the device into said low power consumption mode.
Claim 14
Dependent Claim
119 words
A semiconductor memory device comprising: an internal voltage generator receiving a power supply voltage from an exterior for generating an internal voltage to be supplied to a first internal circuit; and an entry circuit for inactivating said internal voltage generator in response to one or more control signals received from the exterior and entering the device into a low power consumption mode in which the generation of said internal voltage stops, and wherein said entry circuit receives said one or more control signals during said low power consumption mode and exits the device from said low power consumption mode when one or more states of said one or more control signals indicate exit of said low power consumption mode.
Claim 15
Dependent Claim
119 words
A semiconductor memory device comprising: an internal voltage generator receiving a power supply voltage from an exterior for generating an internal voltage to be supplied to a first internal circuit; and an entry circuit for inactivating said internal voltage generator in response to one or more control signals received from the exterior and entering the device into a low power consumption mode in which the generation of said internal voltage stops, and wherein said entry circuit receives said one or more control signals during said low power consumption mode and exits the device from said low power consumption mode when one or more states of said one or more control signals indicate exit of said low power consumption mode.
Claim 16
Dependent Claim
47 words
The semiconductor memory device according to claim 13 , further comprising a reset signal which is activated to initialize a second internal circuit during a period when said internal voltage is lower than a predetermined voltage after the device is exited from said lower power consumption mode.
Claim 17
Dependent Claim
27 words
The semiconductor memory device according to claim 14 , wherein said predetermined voltage is a reference voltage which is generated by stepping down said power supply voltage.
Claim 18
Dependent Claim
51 words
The semiconductor memory device according to claim 13 , further comprising a reset signal which is activated to initialize a second internal circuit during a period when a boost voltage generated in the device is lower than a predetermined voltage after the device is exited from said lower power consumption mode.
Claim 19
Dependent Claim
18 words
The semiconductor memory device according to claim 16 , wherein said predetermined voltage is said power supply voltage.
Claim 20
Dependent Claim
27 words
The semiconductor memory device according to claim 16 , wherein said predetermined voltage is a reference voltage which is generated by stepping down said power supply voltage.
Claim 21
Dependent Claim
59 words
The semiconductor memory device according to claim 13 , further comprising a reset signal which is inactivated to initialize a second internal circuit during a period when at least one of said internal voltage and a boost voltage generated in the device is/are lower than respective predetermined voltages after the device is exited from said lower power consumption mode.
Claim 22
Dependent Claim
50 words
The semiconductor memory device according to claim 13 , further comprising a timer for measuring a predetermined length of time after the device is exited from said lower power consumption mode, and a reset signal which is activated to initialize a second internal circuit during said predetermined length of time.
Claim 23
Dependent Claim
42 words
The semiconductor memory device according to claim 20 , wherein said timer includes a CR time constant circuit; and said predetermined length of time is measured based on a propagation delay time of a signal propagated to said CR time constant circuit.
Claim 24
Dependent Claim
37 words
The semiconductor memory device according to claim 20 , wherein said timer includes a counter which operates during a normal operation; and said predetermined length of time is measured based on a count value of said counter.
Claim 25
Dependent Claim
23 words
The semiconductor memory device according to claim 22 , wherein said counter is a refresh counter which indicates refresh address of memory cells.
Claim 26
Dependent Claim
101 words
A semiconductor memory device comprising: dynamic memory cells; an internal voltage generator for generating an internal voltage to be supplied to a predetermined internal circuit upon receipt of a power supply voltage from an exterior; and an internal voltage detector for detecting a level of said internal voltage and controlling said internal voltage generator according to a detection result, and wherein detection capability of said internal voltage detector is lowered when a control signal is received from an exterior, thereby entering the device into a low power consumption mode, which inactivates function of a refresh operation for said dynamic memory cells.
Claim 27
Dependent Claim
101 words
A semiconductor memory device comprising: dynamic memory cells; an internal voltage generator for generating an internal voltage to be supplied to a predetermined internal circuit upon receipt of a power supply voltage from an exterior; and an internal voltage detector for detecting a level of said internal voltage and controlling said internal voltage generator according to a detection result, and wherein detection capability of said internal voltage detector is lowered when a control signal is received from an exterior, thereby entering the device into a low power consumption mode, which inactivates function of a refresh operation for said dynamic memory cells.
Claim 28
Dependent Claim
40 words
The semiconductor memory device according to claim 24 , wherein said internal voltage generator includes a plurality of units for detecting a level of said internal voltage; and a part of said units suspend(s) during said low power consumption mode.
Claim 29
Dependent Claim
106 words
A semiconductor memory device comprising: an internal voltage generator for generating an internal voltage to be supplied to a predetermined internal circuit upon receipt of a power supply voltage from an exterior, and an internal voltage detector for detecting a level of said internal voltage and controlling said internal voltage generator according to a detection result, and wherein when a control signal is received from the exterior, the absolute value of said internal voltage generated by said internal voltage generator is reduced by lowering the detection level of said internal voltage in said internal voltage detector, thereby entering the device into a low power consumption mode.
Claim 30
Dependent Claim
106 words
A semiconductor memory device comprising: an internal voltage generator for generating an internal voltage to be supplied to a predetermined internal circuit upon receipt of a power supply voltage from an exterior, and an internal voltage detector for detecting a level of said internal voltage and controlling said internal voltage generator according to a detection result, and wherein when a control signal is received from the exterior, the absolute value of said internal voltage generated by said internal voltage generator is reduced by lowering the detection level of said internal voltage in said internal voltage detector, thereby entering the device into a low power consumption mode.
Claim 31
Dependent Claim
80 words
The semiconductor memory device according to claim 26 , further comprising a reference voltage generator for generating a reference voltage, and wherein said internal voltage detector detects the level of said internal voltage by comparing said internal voltage with said reference voltage; and when a control signal is received from the exterior, the detection level of said internal voltage in said internal voltage detector is lowered by decreasing the level of said reference voltage generated by said reference voltage generator.
Claim 32
Independent Claim
75 words
A method of controlling a semiconductor memory device, comprising an internal voltage generator receiving a power supply voltage from an exterior for generating an internal voltage to be supplied to an internal circuit, said method comprising the steps of: inactivating said internal voltage generator in response to one or more control signals received from the exterior; and entering the device into a low power consumption mode in which the generation of said internal voltage stops.
Claim 33
Independent Claim
75 words
A method of controlling a semiconductor memory device, comprising an internal voltage generator receiving a power supply voltage from an exterior for generating an internal voltage to be supplied to an internal circuit, said method comprising the steps of: inactivating said internal voltage generator in response to one or more control signals received from the exterior; and entering the device into a low power consumption mode in which the generation of said internal voltage stops.
Claim 34
Dependent Claim
40 words
The method of controlling a semiconductor memory device according to claim 28 , wherein the device enters into said low power consumption mode when a logical combination of said one or more control signals indicate a low power consumption command.
Claim 35
Dependent Claim
101 words
The method of controlling a semiconductor memory device according to claim 29 , wherein the device enters into said low power consumption mode when a reset signal as a first control signal of said one or more control signals is inactivated and then a chip enable signal as a second control signal of said one or more control signals is activated, said reset signal inactivating said internal circuit and said chip enable signal activating a part of said internal circuit to be operated in a read/write operation, and wherein said reset signal is inactivated when the power supply is switched on.
Claim 36
Independent Claim
120 words
A method of controlling a semiconductor memory device, comprising an internal voltage generator receiving a power supply voltage from an exterior for generating an internal voltage to be supplied to a first internal circuit, said method comprising the steps of: inactivating said internal voltage generator in response to one or more control signals received from the exterior and entering the device into a low power consumption mode to stop the generation of said internal voltage; and receiving said one or more control signals during said low power consumption mode and exiting the device from said low power consumption mode when the one or more states of said one or more control signals indicate exit of said low power consumption mode.
Claim 37
Independent Claim
120 words
A method of controlling a semiconductor memory device, comprising an internal voltage generator receiving a power supply voltage from an exterior for generating an internal voltage to be supplied to a first internal circuit, said method comprising the steps of: inactivating said internal voltage generator in response to one or more control signals received from the exterior and entering the device into a low power consumption mode to stop the generation of said internal voltage; and receiving said one or more control signals during said low power consumption mode and exiting the device from said low power consumption mode when the one or more states of said one or more control signals indicate exit of said low power consumption mode.
Claim 38
Dependent Claim
55 words
The method of controlling a semiconductor memory device according to claim 31 , further comprising the steps of: activating a reset signal which is activated to initialize a second internal circuit during a period when said internal voltage is lower than a predetermined voltage after the device is exited from said lower power consumption mode.
Claim 39
Independent Claim
107 words
A method of controlling a semiconductor memory device comprising dynamic memory cells; an internal voltage generator for generating an internal voltage to be supplied to a predetermined internal circuit upon receipt of a power supply voltage from an exterior; and an internal voltage detector for detecting a level of said internal voltage and controlling said internal voltage generator according to a detection result, further comprising the steps of: lowering the detection capability of said internal voltage detector when a control signal is received from an exterior; and entering the device into a low power consumption mode which inactivates function of a refresh operation of dynamic memory cells.
Claim 40
Independent Claim
107 words
A method of controlling a semiconductor memory device comprising dynamic memory cells; an internal voltage generator for generating an internal voltage to be supplied to a predetermined internal circuit upon receipt of a power supply voltage from an exterior; and an internal voltage detector for detecting a level of said internal voltage and controlling said internal voltage generator according to a detection result, further comprising the steps of: lowering the detection capability of said internal voltage detector when a control signal is received from an exterior; and entering the device into a low power consumption mode which inactivates function of a refresh operation of dynamic memory cells.
Claim 41
Independent Claim
112 words
A method of controlling a semiconductor memory device comprising an internal voltage generator for generating an internal voltage to be supplied to a predetermined internal circuit upon receipt of a power supply voltage from an exterior; and an internal voltage detector for detecting a level of said internal voltage and controlling said internal voltage generator according to a detection result, further comprising the steps of: reducing the absolute value of said internal voltage generated by said internal voltage generator by lowering the detection level of said internal voltage in said internal voltage detector when a control signal is received from the exterior; and entering the device into a low power consumption mode.
Claim 42
Independent Claim
112 words
A method of controlling a semiconductor memory device comprising an internal voltage generator for generating an internal voltage to be supplied to a predetermined internal circuit upon receipt of a power supply voltage from an exterior; and an internal voltage detector for detecting a level of said internal voltage and controlling said internal voltage generator according to a detection result, further comprising the steps of: reducing the absolute value of said internal voltage generated by said internal voltage generator by lowering the detection level of said internal voltage in said internal voltage detector when a control signal is received from the exterior; and entering the device into a low power consumption mode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-05-12 | 2006-11-11 | 2007-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-05-12 | 2010-11-11 | 2011-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-05-12 | 2014-11-11 | 2015-05-13 | $7700.00 | Window Closed / Lapsed |