Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit comprising: a booster for boosting a power supply voltage, and outputting the boosted voltage; an output circuit being supplied with the boosted voltage, generating an output voltage from the boosted voltage, and outputting the output voltage through an output terminal; a reference voltage generator being supplied with the power supply voltage, generating a reference voltage from the power supply voltage, and outputting the reference voltage; a voltage divider being supplied with the output voltage from the output circuit, dividing the output voltage with a predetermined voltage ratio, and outputting the divided voltage; and a differential amplifier being supplied with the reference voltage and the divided voltage, and controlling the output circuit by supplying the output circuit with a voltage which is obtained by performing differential amplification on the reference voltage and the divided voltage according to the power supply voltage, thereby maintaining the output voltage from the output circuit at a predetermined voltage.

Claim 3

The semiconductor integrated circuit of claim 1 wherein said voltage divider is a resistance type voltage divider having a plurality of resistors connected in series.

Claim 4

The semiconductor integrated circuit of claim 1 wherein said voltage divider comprises a plurality of diode-junction type transistors connected in series, each transistor having a gate and a drain connected to each other, and a source connected to a substrate.

Claim 5

The semiconductor integrated circuit of claim 1 wherein said voltage divider comprises: a plurality of capacitors connected in series; and an initialization circuit performing initialization by short-circuiting the both ends of each capacitor.

Claim 6

The semiconductor integrated circuit of claim 1 wherein said voltage divider sets the voltage ratio at different values according to control signals.

Claim 7

The semiconductor integrated circuit of claim 5 wherein said voltage divider comprises: a plurality of resistors connected in series between the output terminal of the output circuit and the ground voltage; at least one transistor having an end connected to any of the nodes between the plural resistors, and the other end connected to the output terminal of the output circuit; a control circuit being supplied with the control signal, and giving a control voltage based on the control signal to a control end of the transistor; and an output terminal for taking out the divided voltage, connected to any of the nodes between the plural resistors.

Claim 8

The semiconductor integrated circuit of claim 5 wherein said voltage divider comprises: a plurality of diode-junction type transistors connected in series between the output terminal of the output circuit and the ground voltage, each transistor having a gate and a drain connected to each other, and a source connected to a substrate; at least one transistor for voltage control, having an end connected to any of the nodes between the plural transistors, and the other end connected to the output terminal of the output circuit; a control circuit being supplied with the control signal, and giving a control voltage based on the control signal to a control end of the transistor for voltage control; and an output terminal for taking out the divided voltage, connected to any of the nodes between the plural transistors.

Claim 9

The semiconductor integrated circuit of claim 5 wherein said voltage divider comprises: a plurality of capacitors connected in series between the output terminal of the output circuit and the ground voltage; at least one transistor having an end connected to any of the nodes between the plural capacitors, and the other end connected to the output terminal of the output circuit; a control circuit being supplied with the control signal, and giving a control voltage based on the control signal to a control end of the transistor; an initialization circuit performing initialization by short-circuiting the both ends of each capacitor; and an output terminal for taking out the divided voltage, connected to any of the nodes between the plural capacitors.

Claim 10

The semiconductor integrated circuit of claim 5 wherein said voltage divider comprises: two first capacitors connected in series between the output terminal of the output circuit and the ground voltage; at least one transistor having an end connected to a node between the first capacitors; at least one second capacitor, as many as said transistor, having an end connected to the transistor, and the other end being grounded; a control circuit being supplied with the control signal, and giving a control voltage based on the control signal to a control end of the transistor; an initialization circuit for initializing the node between the first capacitors; and an output terminal for taking out the divided voltage, connected to the node between the first capacitors.

Claim 11

The semiconductor integrated circuit of claim 1 wherein said output circuit comprises: a first P type MOS transistor having a gate, a source connected to the output terminal of the booster, and a drain connected to the output terminal of the output circuit; a second P type MOS transistor having a gate, a source connected to the output terminal of the booster, and a drain connected to the gate of the first P type MOS transistor; an N type MOS transistor having a source being grounded, a drain connected to the drain of the second P type MOS transistor, and a gate connected to the output terminal of the differential amplifier; and a bias circuit for giving a bias voltage to the gate of the second P type MOS transistor.

Claim 12

The semiconductor integrated circuit of claim 1 wherein said output circuit comprises: a first P type MOS transistor having a gate, a source connected to the output terminal of the booster, and a drain connected to the output terminal of the output circuit; a second P type MOS transistor having a source connected to the output terminal of the booster, and a gate and a drain connected to the gate of the first P type MOS transistor; and an N type MOS transistor having a source being grounded, a drain connected to the drain of the second P type MOS transistor, and a gate connected to the output terminal of the differential amplifier.

Claim 13

The semiconductor integrated circuit of claim 1 wherein said output circuit comprises: a first P type MOS transistor having a gate, a source connected to the output terminal of the booster, and a drain connected to the output terminal of the output circuit; a second P type MOS transistor having a source connected to the output terminal of the booster, a drain connected to the gate of the first P type MOS transistor, and a gate being grounded; and an N type MOS transistor having a source being grounded, a drain connected to the drain of the second P type MOS transistor, and a gate connected to the output terminal of the differential amplifier.

Claim 14

A semiconductor integrated circuit comprising: a negative booster for generating a negative voltage from a power supply voltage, and outputting the negative voltage; an output circuit being supplied with the negative voltage, generating an output voltage from the negative voltage, and outputting the output voltage through an output terminal; a reference voltage generator being supplied with the power supply voltage, generating a reference voltage from the power supply voltage, and outputting the reference voltage; a voltage divider being supplied with the output voltage from the output circuit and the reference voltage, dividing a potential difference between the output voltage and the reference voltage according to a predetermined voltage ratio, and outputting the divided voltage; and a differential amplifier being supplied with the divided voltage and a ground voltage, and controlling the output circuit by supplying the output circuit with a voltage which is obtained by performing differential amplification on the divided voltage and the ground voltage according to the power supply voltage, thereby maintaining the output voltage from the output circuit at a predetermined voltage.

Claim 15

A semiconductor integrated circuit comprising: a negative booster for generating a negative voltage from a power supply voltage, and outputting the negative voltage; an output circuit being supplied with the negative voltage, generating an output voltage from the negative voltage, and outputting the output voltage through an output terminal; a reference voltage generator being supplied with the power supply voltage, generating a reference voltage from the power supply voltage, and outputting the reference voltage; a voltage divider being supplied with the output voltage from the output circuit and the reference voltage, dividing a potential difference between the output voltage and the reference voltage according to a predetermined voltage ratio, and outputting the divided voltage; and a differential amplifier being supplied with the divided voltage and a ground voltage, and controlling the output circuit by supplying the output circuit with a voltage which is obtained by performing differential amplification on the divided voltage and the ground voltage according to the power supply voltage, thereby maintaining the output voltage from the output circuit at a predetermined voltage.

Claim 16

The semiconductor integrated circuit of claim 13 wherein said voltage divider is a resistance type voltage divider having a plurality of resistors connected in series.

Claim 17

The semiconductor integrated circuit of claim 13 wherein said voltage divider comprises a plurality of diode-junction type transistors connected in series, each transistor having a gate and a drain connected to each other, and a source connected to a substrate.

Claim 18

The semiconductor integrated circuit of claim 13 wherein said voltage divider comprises: a plurality of capacitors connected in series; and an initialization circuit performing initialization by short-circuiting the both ends of each capacitor.

Claim 19

The semiconductor integrated circuit of claim 13 wherein said voltage divider sets the voltage ratio at different values according to control signals.

Claim 20

The semiconductor integrated circuit of claim 17 wherein said voltage divider comprises: a plurality of resistors connected in series between the output terminal of the output circuit and the output terminal of the reference voltage generator; at least one transistor having an end connected to any of the nodes between the plural resistors, and the other end connected to the output terminal of the output circuit; a control circuit being supplied with the control signal, and giving a control voltage based on the control signal to a control end of the transistor; and an output terminal for taking out the divided voltage, connected to any of the nodes between the plural resistors.

Claim 21

The semiconductor integrated circuit of claim 17 wherein said voltage divider comprises: a plurality of diode-junction type transistors connected in series between the output end of the output circuit and the output end of the reference voltage generator, each transistor having a gate and a drain connected to each other, and a source connected to a substrate; at least one transistor for voltage control having an end connected to any of the nodes between the plural transistors, and the other end connected to the output end of the output circuit; a control circuit being supplied with the control signal, and giving a control voltage based on the control signal to a control end of the transistor for voltage control; and an output terminal for taking out a divided voltage, connected to any of the nodes between the plural transistors.

Claim 22

The semiconductor integrated circuit of claim 17 wherein said voltage divider comprises: a plurality of capacitors connected in series between the output terminal of the output circuit and the output terminal of the reference voltage generator; at least one transistor having an end connected to any of the nodes between the plural capacitors, and the other end connected to the output terminal of the output circuit; a control circuit being supplied with the control signal, and giving a control voltage based on the control signal to a control end of the transistor; an initialization circuit performing initialization by short-circuiting the both ends of each capacitor; and an output terminal for taking out the divided voltage, connected to any of the nodes between the plural capacitors.

Claim 23

The semiconductor integrated circuit of claim 17 wherein said voltage divider comprises: two first capacitors connected in series between the output terminal of the output circuit and the output terminal of the reference voltage generator; at least one transistor having an end connected to a node between the first capacitors; at least one second capacitor, as many as said transistor, having an end connected to the transistor, and the other end connected to the output terminal of the reference voltage generator; a control circuit being supplied with the control signal, and giving a control voltage based on the control signal to a control end of the transistor; an initialization circuit for initializing the node between the first capacitors; and an output terminal for taking out the divided voltage, connected to the node between the first capacitors.

Claim 24

The semiconductor integrated circuit of claim 13 wherein said output circuit comprises: a first N type MOS transistor having a gate, a source connected to the output terminal of the negative booster, and a drain connected to the output terminal of the output circuit; a second N type MOS transistor having a gate, a source connected to the output terminal of the negative booster, and a drain connected to the gate of the first N type MOS transistor; a P type MOS transistor having a source connected to the power supply voltage, a drain connected to the drain of the second N type MOS transistor, and a gate connected to the output terminal of the differential amplifier; and a bias circuit for giving a bias voltage to the gate of the second N type MOS transistor.

Claim 25

The semiconductor integrated circuit of claim 13 wherein said output circuit comprises: a first N type MOS transistor having a gate, a source connected to the output terminal of the negative booster, and a drain connected to the output terminal of the output circuit; a second N type MOS transistor having a source connected to the output terminal of the negative booster, and a gate and a drain connected to the gate of the first N type MOS transistor; and a P type MOS transistor having a source connected to the power supply voltage, a drain connected to the drain of the second N type MOS transistor, and a gate connected to the output terminal of the differential amplifier.

Claim 26

The semiconductor integrated circuit of claim 13 wherein said output circuit comprises: a first N type MOS transistor having a gate, a source connected to the output terminal of the negative booster, and a drain connected to the output terminal of the output circuit; a second N type MOS transistor having a source connected to the output terminal of the negative booster, a drain connected to the gate of the first N type MOS transistor, and a gate being grounded; and a P type MOS transistor having a source connected to the power supply voltage, a drain connected to the drain of the second N type Mos transistor, and a gate connected to the output terminal of the differential amplifier.

Claim 27

A semiconductor integrated circuit comprising: a booster for boosting a power supply voltage, and outputting the boosted voltage; a first output circuit being supplied with the boosted voltage, generating an output voltage from the boosted voltage, and outputting the output voltage through an output terminal; a reference voltage generator being supplied with the power supply voltage, generating a reference voltage from the power supply voltage, and outputting the reference voltage; a first voltage divider being supplied with the output voltage from the first output circuit, dividing the output voltage according to a predetermined voltage ratio, and outputting the divided voltage; a first differential amplifier being supplied with the reference voltage and the divided voltage from the first voltage divider, and controlling the first output circuit by supplying it with a voltage which is obtained by performing differential amplification on the reference voltage and the divided voltage according to the power supply voltage, thereby maintaining the output voltage from the first output circuit at a predetermined voltage; a negative booster for generating a negative voltage from the power supply voltage, and outputting the negative voltage; a second output circuit being supplied with the negative voltage, generating an output voltage from the negative voltage, and outputting the output voltage through an output terminal; a second voltage divider being supplied with the output voltage from the second output circuit and the reference voltage, dividing a potential difference between the output voltage and the reference voltage according to a predetermined voltage ratio, and outputting the divided voltage; and a second differential amplifier being supplied with the divided voltage from the second voltage divider and the ground voltage, and controlling the second output circuit by supplying it with a voltage which is obtained by performing differential amplification on the divided voltage and the reference voltage according to the power supply voltage, thereby maintaining the output voltage from the second output circuit at a predetermined voltage.

Claim 28

A semiconductor integrated circuit comprising: a booster for boosting a power supply voltage, and outputting the boosted voltage; a first output circuit being supplied with the boosted voltage, generating an output voltage from the boosted voltage, and outputting the output voltage through an output terminal; a reference voltage generator being supplied with the power supply voltage, generating a reference voltage from the power supply voltage, and outputting the reference voltage; a first voltage divider being supplied with the output voltage from the first output circuit, dividing the output voltage according to a predetermined voltage ratio, and outputting the divided voltage; a first differential amplifier being supplied with the reference voltage and the divided voltage from the first voltage divider, and controlling the first output circuit by supplying it with a voltage which is obtained by performing differential amplification on the reference voltage and the divided voltage according to the power supply voltage, thereby maintaining the output voltage from the first output circuit at a predetermined voltage; a negative booster for generating a negative voltage from the power supply voltage, and outputting the negative voltage; a second output circuit being supplied with the negative voltage, generating an output voltage from the negative voltage, and outputting the output voltage through an output terminal; a second voltage divider being supplied with the output voltage from the second output circuit and the reference voltage, dividing a potential difference between the output voltage and the reference voltage according to a predetermined voltage ratio, and outputting the divided voltage; and a second differential amplifier being supplied with the divided voltage from the second voltage divider and the ground voltage, and controlling the second output circuit by supplying it with a voltage which is obtained by performing differential amplification on the divided voltage and the reference voltage according to the power supply voltage, thereby maintaining the output voltage from the second output circuit at a predetermined voltage.

Claim 29

The semiconductor integrated circuit of claim 25 wherein said first voltage divider comprises: a plurality of diode-junction type transistors connected in series between the output terminal of the first output circuit and the ground voltage, each transistor having a gate and a drain connected to each other, and a source connected to a substrate; at least one transistor for voltage control having an end connected to any of the nodes between the plural transistors, and the other end connected to the output terminal of the first output circuit; a control circuit being supplied with the control signal, and giving a control voltage based on the control -signal to a control end of the transistor for voltage control; and an output terminal for taking out the divided voltage, connected to any of the nodes between the plural transistors.

Claim 30

The semiconductor integrated circuit of claim 25 wherein said second voltage divider comprises: a plurality of diode-junction type transistors connected in series between the output terminal of the second output circuit and the output terminal of the reference voltage generator, each transistor having a gate and a drain connected to each other, and a source connected to a substrate; at least one transistor for voltage control having an end connected to any of the nodes between the plural transistors, and the other end connected to the output terminal of the second output circuit; a control circuit being supplied with the control signal, and giving a control voltage based on the control signal to a control end of the transistor for voltage control; and an output terminal for taking out the divided voltage, connected to any of the nodes between the plural transistors.

Claim 31

The semiconductor integrated circuit of claim 25 further comprising: a voltage follower circuit being supplied with the output from the reference voltage generator; and said second voltage divider being supplied with the output voltage from the voltage follower circuit, as the reference voltage, instead of the output from the reference voltage generator.