US7122435B2
Expired / Lapsed
US
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Methods, systems and structures for forming improved transistors
Assignee: Texas Instruments Inc
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Filing: 2004-08-02
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Granted: 2006-10-17
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Expires: 2024-08-02
Abstract
Abstract A method ( 100 ) of forming a transistor includes forming a gate structure ( 106, 108 ) over a semiconductor body and forming recesses ( 112 ) substantially aligned to the gate structure in the semiconductor body. Amorphous silicon regions are then formed ( 114 ) in the recesses. The amorphous silicon regions are re-crystallized. Sidewall spacers are formed ( 118 ) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body ( 120 ) after forming the sidewall spacers. The re-crystallized silicon regions formed in the recesses reside close to the transistor channel and serve to facilitate improved carrier mobility in NMOS type transistor devices.
Inventors
- 👤 PR Chidambaram
- 👤 Haowen Bu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:27
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/791; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/601; H10D30/797; H10D62/00; H10D62/01; H10D62/021; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/017; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
79 words
A method of forming a transistor, comprising: forming a gate structure over a semiconductor body; forming amorphous regions of silicon doped with a Group IVa element aligned to the gate structure in the semiconductor body; re-crystallizing the amorphous regions of silicon to form doped substitutional crystalline regions; implanting source and drain regions in the doped crystalline regions; forming recesses substantially aligned to the gate structure in the semiconductor body; and forming the amorphous regions of silicon in the recesses.
Claim 2
Independent Claim
79 words
A method of forming a transistor, comprising: forming a gate structure over a semiconductor body; forming amorphous regions of silicon doped with a Group IVa element aligned to the gate structure in the semiconductor body; re-crystallizing the amorphous regions of silicon to form doped substitutional crystalline regions; implanting source and drain regions in the doped crystalline regions; forming recesses substantially aligned to the gate structure in the semiconductor body; and forming the amorphous regions of silicon in the recesses.
Claim 3
Dependent Claim
45 words
The method of claim 1 , wherein the step of forming amorphous regions of silicon comprises the steps of: depositing regions of silicon doped with a Group IVa element; and implanting a dopant into the regions of silicon to form the amorphous regions of silicon.
Claim 4
Dependent Claim
27 words
The method of claim 1 , wherein the step of forming amorphous regions of silicon comprises a gas ion beam deposition of the amorphous regions of silicon.
Claim 5
Dependent Claim
23 words
The method of claim 1 wherein the step of re-crystallizing the amorphous regions of silicon includes thermal processing the amorphous regions of silicon.
Claim 6
Dependent Claim
36 words
The method of claim 1 , wherein the group IVa dopant is carbon and the doped silicon regions contains in the range of about 0.2 atomic percent substitutional carbon to about 2 percent substitutional atomic carbon.
Claim 7
Dependent Claim
24 words
The method of claim 1 , wherein the recesses have a depth of about 30 nm or more and about 110 nm or less.
Claim 8
Dependent Claim
32 words
The method of claim 1 , further comprising performing a thermal process after implanting the source and drain regions, wherein the source and drain regions diffuse laterally due to the thermal process.
Claim 9
Independent Claim
115 words
A method of forming an NMOS and a PMOS transistor concurrently, comprising: forming a gate structure over a semiconductor body in an NMOS region and a PMOS region, respectively; forming recesses substantially aligned to the gate structures in the semiconductor body in both the NMOS and PMOS regions; forming amorphous regions of silicon doped with a Group IVa element in the recesses; crystallizing the amorphous regions of silicon to form substitutional crystallized regions of silicon; forming sidewall spacers over lateral edges of the gate structures; and implanting n-type source and drain regions in the NMOS region and p-type source and drain regions in the PMOS region of the semiconductor body after forming the sidewall spacers.
Claim 10
Independent Claim
115 words
A method of forming an NMOS and a PMOS transistor concurrently, comprising: forming a gate structure over a semiconductor body in an NMOS region and a PMOS region, respectively; forming recesses substantially aligned to the gate structures in the semiconductor body in both the NMOS and PMOS regions; forming amorphous regions of silicon doped with a Group IVa element in the recesses; crystallizing the amorphous regions of silicon to form substitutional crystallized regions of silicon; forming sidewall spacers over lateral edges of the gate structures; and implanting n-type source and drain regions in the NMOS region and p-type source and drain regions in the PMOS region of the semiconductor body after forming the sidewall spacers.
Claim 11
Dependent Claim
44 words
The method of claim 8 wherein the step of forming amorphous regions of silicon comprises the steps of: depositing regions of silicon doped with a Group IVa element; and implanting a dopant into the regions of silicon to form the amorphous regions of silicon.
Claim 12
Dependent Claim
26 words
The method of claim 8 wherein the step of forming amorphous regions of silicon comprises a gas ion beam deposition of the amorphous regions of silicon.
Claim 13
Dependent Claim
22 words
The method of claim 8 wherein the step of crystallizing the amorphous regions of silicon includes cooling the amorphous regions of silicon.
Claim 14
Dependent Claim
38 words
The method of claim 8 , further comprising forming offset spacers on the lateral edges of the gate structures before forming the recesses, wherein the recesses are aligned in the semiconductor body with respect to the offset spacers.
Claim 15
Dependent Claim
33 words
The method of claim 12 , wherein the recesses are offset from the lateral edges of the gate structure a distance of about 10 nm or more and about 50 nm or less.
Claim 16
Dependent Claim
29 words
The method of claim 8 , further comprising implanting n-type extension regions in the NMOS region and p-type extension regions in the PMOS region into the crystallized silicon regions.
Claim 17
Dependent Claim
30 words
The method of claim 8 , wherein the group IVa dopant is carbon in the range of about 0.2 atomic percent substitutional carbon to about 2 atomic percent substitutional carbon.
Claim 18
Dependent Claim
24 words
The method of claim 8 , wherein the recesses have a depth of about 30 nm or more and about 110 nm or less.
Claim 19
Dependent Claim
109 words
The method of claim 16 , further comprising: forming offset spacers on the lateral edges of the gate structures before forming the recesses, wherein the recesses are aligned in the semiconductor body with respect to the offset spacers; performing an n-type extension region implant in the NMOS region and a p-type extension region implant in the PMOS region, respectively, after formation of the offset spacers and before forming the recesses; and performing a thermal process after the extension region implant and before forming the recesses, wherein the extension regions slightly diffuse laterally in response thereto such that edges thereof extend below the offset spacers toward the respective gate structures.
Claim 20
Dependent Claim
52 words
The method of claim 8 , further comprising performing a thermal process after implanting the n-type source and drain regions in the NMOS region and the p-type source and drain regions in the PMOS region, respectively, wherein the n-type and p-type source and drain regions diffuse laterally due to the thermal process.
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