Patent US7119006B2 successfully refreshed from Google Patents.
US7119006B2
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US
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Via formation for damascene metal conductors in an integrated circuit
Assignee: Texas Instruments Inc
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Filing: 2002-11-26
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Granted: 2006-10-10
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Expires: 2022-11-26
Abstract
Abstract A method of fabricating an integrated circuit, having copper metallization formed by a dual damascene process, is disclosed. A layered insulator structure is formed over a first conductor ( 22 ), within which a second conductor ( 40 ) is formed to contact the first conductor. The layered insulator structure includes a via etch stop layer ( 24 ), an interlevel dielectric layer ( 26 ), a trench etch stop layer ( 28 ), an intermetal dielectric layer ( 30 ), and a hardmask layer ( 32 ). The interlevel dielectric layer ( 26 ) and the intermetal dielectric layer ( 30 ) are preferably of the same material. A via is partially etched through the intermetal dielectric layer ( 30 ), and through an optional trench etch stop layer ( 28 ). A trench location is then defined by photoresist ( 38 ), and this trench location is transferred to the hardmask layer ( 32 ). Simultaneous etching of the trench through intermetal dielectric layer ( 30 ), stopping on the trench etch stop layer ( 28 ) if present, simultaneously with the etching of the remainder of the via through the interlevel dielectric layer ( 26 ) that stops on the via etch stop layer ( 24 ), is then performed. After clearing the via etch stop layer ( 24 ) from the via bottom, a copper conductor ( 40 ) is then formed into the trench and via, for example by electroplating and planarization by chemical mechanical polishing over a barrier layer ( 41 ).
Inventors
- 👤 Robert Kraft
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:10
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/084; H10W20/085; H10W20/088
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
249 words
A method of forming a metal conductor in an integrated circuit, comprising the steps of: forming a via etch stop layer over a first conductor; forming an interlevel dielectric layer over the via etch stop layer; forming an intermetal dielectric layer over the interlevel dielectric layer; forming a hardmask layer over the intermetal dielectric layer; then etching through the hardmask layer and the intermetal dielectric layer at a via location; then, defining a trench location with a trench mask layer, the trench location overlapping at least partially over the etched portion of the intermetal dielectric layer, wherein the step of defining a trench location with a trench mask layer comprises: forming a masking layer comprised of photoresist over the hardmask layer; patterning the masking layer over the hardmask layer, to define the trench location; etching the hardmask layer at the trench location, using the patterned masking layer as a mask; and removing the patterned masking layer; then simultaneously etching through the intermetal dielectric layer at the trench location and through the interlevel dielectric layer at the via location, the etching at the via location effectively stopping at the via etch stop layer, the simultaneous etching forming a trench in the intermetal dielectric layer at the trench location that is contiguous with a via through the interlevel dielectric layer at the via location; removing the via etch stop layer at the via location; and then forming a second conductor within the trench and via, in contact with the first conductor.
Claim 2
Independent Claim
249 words
A method of forming a metal conductor in an integrated circuit, comprising the steps of: forming a via etch stop layer over a first conductor; forming an interlevel dielectric layer over the via etch stop layer; forming an intermetal dielectric layer over the interlevel dielectric layer; forming a hardmask layer over the intermetal dielectric layer; then etching through the hardmask layer and the intermetal dielectric layer at a via location; then, defining a trench location with a trench mask layer, the trench location overlapping at least partially over the etched portion of the intermetal dielectric layer, wherein the step of defining a trench location with a trench mask layer comprises: forming a masking layer comprised of photoresist over the hardmask layer; patterning the masking layer over the hardmask layer, to define the trench location; etching the hardmask layer at the trench location, using the patterned masking layer as a mask; and removing the patterned masking layer; then simultaneously etching through the intermetal dielectric layer at the trench location and through the interlevel dielectric layer at the via location, the etching at the via location effectively stopping at the via etch stop layer, the simultaneous etching forming a trench in the intermetal dielectric layer at the trench location that is contiguous with a via through the interlevel dielectric layer at the via location; removing the via etch stop layer at the via location; and then forming a second conductor within the trench and via, in contact with the first conductor.
Claim 3
Dependent Claim
98 words
The method of claim 1 , further comprising: forming a trench etch stop layer over the interlevel dielectric layer; wherein the step of forming the intermetal dielectric layer forms is performed after the step of forming the trench etch stop layer; wherein the step of etching through the intermetal dielectric layer also etches through the trench etch stop layer; and wherein the step of simultaneously etching through the intermetal dielectric layer at the trench location and through the interlevel dielectric layer at the via location also, at the trench location, effectively stops at the trench etch stop layer.
Claim 4
Dependent Claim
17 words
The method of claim 1 , further comprising etching the hardmask layer to define the via location.
Claim 5
Dependent Claim
62 words
The method of claim 1 , wherein the step of forming the masking layer comprises: forming a bottom antireflective coating layer over the etched hardmask layer; forming a photoresist layer over the bottom antireflective coating layer; patterning the photoresist layer to remove a portion thereof at the trench location, leaving the remainder of the patterned photoresist layer as the patterned masking layer.
Claim 6
Dependent Claim
30 words
The method of claim 4 , wherein the step of removing the patterned masking layer removes both the patterned photoresist layer and remaining portions of the bottom antireflective coating layer.
Claim 7
Dependent Claim
23 words
The method of claim 1 , wherein the intermetal dielectric layer and interlevel dielectric layer are comprised of different materials from one another.
Claim 8
Dependent Claim
24 words
The method of claim 1 , wherein the intermetal dielectric layer and interlevel dielectric layer are comprised of the same material as one another.
Claim 9
Dependent Claim
12 words
The method of claim 1 , wherein the second conductor comprises copper.
Claim 10
Dependent Claim
52 words
The method of claim 8 , wherein the step of forming a second conductor comprises: electroplating a layer of metal, comprising copper, the layer of metal extending into the trench and via and overlying the intermetal dielectric layer; and planarizing the layer of metal to remove portions overlying the intermetal dielectric layer.
Claim 11
Dependent Claim
16 words
The method of claim 9 , wherein the planarizing step is performed by chemical mechanical polishing.
Claim 12
Dependent Claim
171 words
The method of claim 1 , further comprising: forming a via etch stop layer over the second conductor; forming an interlevel dielectric layer over the via etch stop layer; forming a intermetal dielectric layer over the interlevel dielectric layer; then etching through the intermetal dielectric layer at a via location; defining a trench location with a trench mask layer, the trench location overlapping at least partially over the etched portion of the intermetal dielectric layer; then simultaneously etching through the intermetal dielectric layer at the trench location and through the interlevel dielectric layer at the via location, the etching at the via location effectively stopping at the via etch stop layer, the simultaneous etching forming a trench in the intermetal dielectric layer at the trench location that is contiguous with a via through the interlevel dielectric layer at the via location; removing the via etch stop layer at the via location; and then forming a third conductor within the trench and via, in contact with a portion of the second conductor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-10-09 | 2010-04-10 | 2010-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-10-09 | 2014-04-10 | 2014-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-10-09 | 2018-04-10 | 2018-10-10 | $7700.00 | Window Closed / Lapsed |