← Back to Patent Explorer
US6448176B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Dual damascene processing for semiconductor chip interconnects

Assignee: GlobalFoundries Inc
•
Filing: 2000-10-30
•
Granted: 2002-09-10
•
Expires: 2020-10-30
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The present invention relates to lithographic methods for forming a dual relief pattern in a substrate, and the application of such methods to fabricating multilevel interconnect structures in semiconductor chips by a Dual Damascene process in which dual relief cavities formed in a dielectric are filled with conductive material to form the wiring and via levels. The invention comprises a twice patterned single mask layer Dual Damascene process modified by the addition of an easy-to-integrate sidewall liner to protect organic interlevel and intralevel dielectrics from potential damage induced by photoresist stripping steps during lithographic rework. The invention further comprises a method for forming a dual pattern hard mask which may be used to form dual relief cavities for use in Dual Damascene processing, said dual pattern hard mask comprising a first set of one or more layers with a first pattern, and a second set of one or more layers with a second pattern.

Inventors

  • 👤 Alfred Grill
  • 👤 John Patrick Hummel
  • 👤 Christopher Vincent Jahnes
  • 👤 Vishnubhai Vitthalbhai Patel
  • 👤 Katherine Lynn Saenger

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 23:36
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/084; H10W20/087; H10W20/088; H10W20/074; H10W20/076; H10W20/0765; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/945

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 58 words
A patterning method utilizing a dual pattern hard mask comprising a first set of one or more mask layer with a first pattern, and a second set of one or more mask layer with a second pattern, wherein mask layer materials of said first set include materials selected from the group consisting of SiCOH compounds and Sic-based dielectrics.
Claim 2
Dependent Claim 58 words
A patterning method utilizing a dual pattern hard mask comprising a first set of one or more mask layer with a first pattern, and a second set of one or more mask layer with a second pattern, wherein mask layer materials of said first set include materials selected from the group consisting of SiCOH compounds and Sic-based dielectrics.
Claim 3
Dependent Claim 27 words
The patterning method of claim 1 wherein mask layer materials of said second set include materials selected from the group consisting of SiCOH compounds and SiC-based dielectrics.
Claim 4
Dependent Claim 18 words
The patterning method of claim 1 wherein mask layer materials of said first and second sets are different.
Claim 5
Dependent Claim 19 words
The patterning method of claim 1 wherein mask layer materials of said first and second sets are the same.
Claim 6
Dependent Claim 23 words
The patterning method of claim 1 wherein at least one set of mask layer is formed by sequential deposition of each constituent layer.

References Cited (Backward Citations)

US5821169A Cited
US6103632A Cited
US6054384A Cited
US6127263A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2005-09-09 2006-03-11 2006-09-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2009-09-09 2010-03-11 2010-09-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2013-09-09 2014-03-11 2014-09-10 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag