US7046059B2 — Delay locked loop and its control method

Claim 1

Independent Claim 138 words

A delay locked loop (DLL) capable of correcting a duty ratio of a clock signal comprising: a clock buffer which receives an external clock signal for outputting a rising edge clock signal; a delay means for delaying the rising edge clock signal based on a first comparison signal in order to generate a first internal clock signal, a second internal clock signal, a first delay locking signal and a second delay locking signal; a duty correction means for receiving the first and the second internal clock signals and the first and the second delay locking signals and generating a delay locked clock signal by correcting a duty cycle of the external clock signal; and a clock feed-back unit for receiving the delay locked clock signal and the external clock signal in order to generate the first comparison signal.

Claim 2

Dependent Claim 138 words

A delay locked loop (DLL) capable of correcting a duty ratio of a clock signal comprising: a clock buffer which receives an external clock signal for outputting a rising edge clock signal; a delay means for delaying the rising edge clock signal based on a first comparison signal in order to generate a first internal clock signal, a second internal clock signal, a first delay locking signal and a second delay locking signal; a duty correction means for receiving the first and the second internal clock signals and the first and the second delay locking signals and generating a delay locked clock signal by correcting a duty cycle of the external clock signal; and a clock feed-back unit for receiving the delay locked clock signal and the external clock signal in order to generate the first comparison signal.

Claim 3

Dependent Claim 70 words

The DLL as recited in claim 1 , wherein the clock feed-back unit includes: a delay model unit which delays the delay locked clock signal for a predetermined delay time to generate a feed-backed clock signal; and a first phase detector which receives the external clock signal and the feed-backed clock signal to generate the first Comparison signal comparing phases of the external clock signal and the feed-backed clock signal.

Claim 4

Dependent Claim 154 words

The DLL as recited in claim 2 , wherein the delay means includes: a delay line controller which receives the first comparison signal and the first and the second delay locking signals to generate a first delay line control signal and a second delay line control signal; a first delay line which delays the rising edge clock signal based on the first delay line control signal in order to generate the first internal clock signal; a second delay line which delays the rising edge clock signal based on the second delay line control signal and inverts the delayed rising edge clock signal in order to generate the second internal clock signal; and a locking detector which receives the first comparison signal and determines whether or not the first and the second delay lines are delay locked based on the first comparison signal in order to generate the first and the second delay locking signal.

Claim 5

Dependent Claim 138 words

The DLL as recited in claim 3 , wherein the duty correction means includes: a second phase detector which receives inverted signals of the first and the second internal clock signals and determines which one of falling edges of the received signals leads the other in order to generate a second comparison signal; a weight controller which receives the second comparison signal and the first and the second delay locking signals in order to generate a weight value; and a phase mixer which receives the first and the second internal clock signals to generate the delay locked clock signal by mixing phases applying the weight value to the second internal clock signal and a second weight value to the first internal clock signal, wherein the second weight value is a value of subtracting the weight value from 1.

Claim 6

Dependent Claim 32 words

The DLL as recited in claim 4 , wherein the weight value includes a first selection signal, a second selection signal, a first selection bar signal and a second selection bar signal.

Claim 7

Dependent Claim 42 words

The DLL as recited in claim 5 , wherein the weight value is determined based on logic states of the first selection signal, the second selection signal, the first selection bar signal, the second selection bar signal and the second comparison signal.

Claim 8

Dependent Claim 78 words

The DLL as recited in claim 6 , wherein the phase mixer includes: a first phase selector for correcting a phase of the first internal clock signal based on the first and the second selection signals and the first and the second selection bar signals; and a second phase selector for correcting a phase of the second internal clock signal based on the first and the second selection signals and the first and the second selection bar signals.

Claim 9

Dependent Claim 40 words

The DLL as recited in claim 7 , wherein the first phase selector includes a plurality of unit phase mixers each of which receives the first and the second selection signals or the first and the second selection bar signals.

Claim 10

Dependent Claim 147 words

The DLL as recited in claim 8 , wherein each of the plurality of unit phase mixers includes: a first PMOS transistor whose source and gate are respectively connected to a power supply voltage and one of the first and the second internal clock signals; a second PMOS transistor whose source and gate are respectively connected to a drain of the first PMOS transistor and one of the first and the second selection signals and the first and the second selection bar signals; a first NMOS transistor whose source and gate are respectively connected to a ground and one of the first and the second internal clock signals; and a second NMOS transistor whose drain and gate are respectively connected to a grain of the second PMOS transistor and one of the first and the second selection signals and the first and the second selection bar signals.

Claim 11

Dependent Claim 139 words

A delay locked loop (DLL) capable of correcting a duty ratio of a clock signal comprising: a clock buffer which receives an external clock signal for outputting a rising edge clock signal; a delay means for delaying the rising edge clock signal based on a first comparison signal in order to generate a first internal clock signal, a second internal clock signal, a first delay locking signal and a second delay locking signal; a duty correction means for receiving the first and the second internal clock signals and the first and the second delay locking signals and generating a delay locked clock signal by correcting a duty cycle of the external clock signal; and a clock feed-back unit for receiving the delay locked clock signal and the rising edge clock signal in order to generate the first comparison signal.

Claim 12

Dependent Claim 139 words

A delay locked loop (DLL) capable of correcting a duty ratio of a clock signal comprising: a clock buffer which receives an external clock signal for outputting a rising edge clock signal; a delay means for delaying the rising edge clock signal based on a first comparison signal in order to generate a first internal clock signal, a second internal clock signal, a first delay locking signal and a second delay locking signal; a duty correction means for receiving the first and the second internal clock signals and the first and the second delay locking signals and generating a delay locked clock signal by correcting a duty cycle of the external clock signal; and a clock feed-back unit for receiving the delay locked clock signal and the rising edge clock signal in order to generate the first comparison signal.

Claim 13

Dependent Claim 73 words

The DLL as recited in claim 10 , wherein the clock feed-back unit includes: a delay model unit which delays the delay locked clock signal for a predetermined delay time to generate a feed-backed clock signal; and a first phase detector which receives the rising edge clock signal and the feed-backed clock signal to generate the first comparison signal by comparing phases of the rising edge clock signal and the feed-backed clock signal.

Claim 14

Dependent Claim 154 words

The DLL as recited in claim 11 , wherein the delay means includes: a delay line controller which receives the first comparison signal and the first and these cond delay locking signals to generate a first delay line control signal and a second delay line control signal; a first delay line which delays the rising edge clock signal based on the first delay line control signal in order to generate the first internal clock signal; a second delay line which delays the rising edge clock signal based on the second delay line control signal and inverts the delayed rising edge clock signal in order to generate the second internal clock signal; and a locking detector which receives the first comparison signal and determines whether or not the first and the second delay lines are delay locked based on the first comparison signal in order to generate the first and the second delay locking signal.

Claim 15

Dependent Claim 137 words

The DLL as recited in claim 12 , wherein the duty correction means includes: a second phase detector which receives inverted signals of the first and the second internal clock signals and determines which one of falling edges of the received signals leads the other in order to generate a second comparison signal; weight controller which receives the second comparison signal and the first and the second delay locking signals in order to generate a weight value; and a phase mixer which receives the first and the second internal clock signals to generate the delay locked clock signal by mixing phases applying the weight value to the second internal clock signal and a second weight value to the first internal clock signal, wherein the second weight value is a value of subtracting the weight value from 1.

Claim 16

Dependent Claim 32 words

The DLL as recited in claim 13 , wherein the weight value includes a first selection signal, a second selection signal, a first selection bar signal and a second selection bar signal.

Claim 17

Dependent Claim 42 words

The DLL as recited in claim 14 , wherein the weight value is determined based on logic states of the first selection signal, the second selection signal, the first selection bar signal, the second selection bar signal and the second comparison signal.

Claim 18

Dependent Claim 78 words

The DLL as recited in claim 15 , wherein the phase mixer includes: a first phase selector for correcting a phase of the first internal clock signal based on the first and the second selection signals and the first and the second selection bar signals; and a second phase selector for correcting a phase of the second internal clock signal based on the first and the second selection signals and the first and the second selection bar signals.

Claim 19

Dependent Claim 40 words

The DLL as recited in claim 16 , wherein the first phase selector includes a plurality of unit phase mixers each of which receives the first and the second selection signals or the first and the second selection bar signals.

Claim 20

Dependent Claim 146 words

The DLL as recited in claim 17 , wherein each of the plurality of unit phase mixers includes: a first PMOS transistor whose source and gate are respectively connected to a power supply voltage and one of the first and the second internal clock signals; a second PMOS transistor whose source and gate are respectively connected to a drain of the first PMOS transistor and one of the first and the second selection signals and the first and the second selection bar signals; a first NMOS transistor whose source and gate are respectively connected to a ground and one of the first and the second internal clock signals; and a second NMOS transistor whose drain and gate are respectively connected a grain of the second PMOS transistor and one of the first and the second selection signals and the first and the second selection bar signals.

Claim 21

Dependent Claim 160 words

A delay locked loop (DLL) capable of correcting duty ratio of a clock signal comprising: a first clock buffer which receives an external clock signal for outputting a first rising edge clock signal; a second clock buffer which receives the external clock signal for outputting a second rising edge clock signal; a delay means for delaying the first and second rising edge clock signal based on a first comparison signal in order to generate a first internal clock signal, a second internal clock signal, a first delay locking signal and a second delay locking signal; a duty correction means for receiving the first and the second internal clock signals and the first and the second delay locking signals and generating a delay locked clock signal by correcting a duty cycle of the external clock signal; and a clock feed-back unit which receives the delay locked clock signal and the external clock signal in order to generate the first comparison signal.

Claim 22

Dependent Claim 160 words

A delay locked loop (DLL) capable of correcting duty ratio of a clock signal comprising: a first clock buffer which receives an external clock signal for outputting a first rising edge clock signal; a second clock buffer which receives the external clock signal for outputting a second rising edge clock signal; a delay means for delaying the first and second rising edge clock signal based on a first comparison signal in order to generate a first internal clock signal, a second internal clock signal, a first delay locking signal and a second delay locking signal; a duty correction means for receiving the first and the second internal clock signals and the first and the second delay locking signals and generating a delay locked clock signal by correcting a duty cycle of the external clock signal; and a clock feed-back unit which receives the delay locked clock signal and the external clock signal in order to generate the first comparison signal.

Claim 23

Dependent Claim 27 words

The DLL as recited in claim 19 , wherein the second 20 rising edge clock signal is an inverted signal of the first rising edge clock signal.

Claim 24

Dependent Claim 71 words

The DLL as recited in claim 20 , wherein the clock feed-back unit includes: a delay model unit which delays the delay locked clock signal for a predetermined delay time to generate a feed-backed clock signal; and a first phase detector which receives the external clock signal and the feed-backed clock signal to generate the first comparison signal by comparing phases of the external clock signal and the feed-backed clock signal.

Claim 25

Dependent Claim 148 words

The DLL as recited in claim 21 , wherein the delay means includes: a delay line controller which receives the first comparison signal and the first and the second delay locking signals to generate a first delay line control signal and a second delay line control signal; a first delay line which delays the first rising edge clock signal based on the first delay line control signal in order to generate the first internal clock signal; a second delay line which delays the second rising edge clock signal based on the second delay line control signal in order to generate the second internal clock signal; and a locking detector which receives the first comparison signal and determines whether or not the first and the second delay lines are delay locked based on the first comparison signal in order to generate the first and the second delay locking signal.

Claim 26

Dependent Claim 138 words

The DLL as recited in claim 22 , wherein the duty correction means includes: a second phase detector which receives inverted signals of the first and the second internal clock signals and determines which one of falling edges of the received signals leads the other in order to generate a second comparison signal; a weight controller which receives the second comparison signal and the first and the second delay locking signals in order to generate a weight value; and a phase mixer which receives the first and the second internal clock signals to generate the delay locked clock signal by mixing phases applying the weight value to the second internal clock signal and a second weight value to the first internal clock signal, wherein the second weight value is a value of subtracting the weight value from 1.

Claim 27

Dependent Claim 32 words

The DLL as recited in claim 23 , wherein the weight value includes a first selection signal, a second selection signal, a first selection bar signal and a second selection bar signal.

Claim 28

Dependent Claim 42 words

The DLL as recited in claim 24 , wherein the weight value is determined based on logic states of the first selection signal, the second selection signal, the first selection bar signal, the second selection bar signal and the second comparison signal.

Claim 29

Dependent Claim 78 words

The DLL as recited in claim 25 , wherein the phase mixer includes: a first phase selector for correcting a phase of the first internal clock signal based on the first and the second selection signals and the first and the second selection bar signals; and a second phase selector for correcting a phase of the second internal clock signal based on the first and the second selection signals and the first and the second selection bar signals.

Claim 30

Dependent Claim 40 words

The DLL as recited in claim 26 , wherein the first phase selector includes a plurality of unit phase mixers each of which receives the first and the second selection signals or the first and the second selection bar signals.

Claim 31

Dependent Claim 146 words

The DLL as recited in claim 27 , wherein each of the plurality of unit phase mixers includes: a first PMOS transistor whose source and gate are respectively connected to a power supply voltage and one of the first and the second internal clock signals; a second PMOS transistor whose source and gate are respectively connected to a drain of the first PMOS transistor and one of the first and the second selection signals and the first and the second selection bar signals; a first NMOS transistor whose source and gate are respectively connected to a ground and one of the first and the second internal clock signals; and a second NMOS transistor whose drain and gate are respectively connected to a grain the second PMOS transistor and one of the first and the second selection signals and the first and the second selection bar signals.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2009-05-15	2009-11-14	2010-05-16	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2013-05-15	2013-11-14	2014-05-16	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2017-05-15	2017-11-14	2018-05-16	$7700.00	Window Closed / Lapsed

Delay locked loop and its control method

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