Semiconductor integrated circuit device and delay-locked loop device

Claim 2

A semiconductor integrated circuit device, comprising: an input buffer for receiving a clock signal applied thereto; a frequency dividing circuit, receiving a clock signal output from said input buffer, for performing frequency division of the clock signal to output a frequency-divided clock signal; a first delay-locked loop circuit including: a first delay line, receiving the frequency-divided clock signal output from said frequency dividing circuit; for outputting a signal obtained by delaying the frequency-divided clock signal, from an output tap selected front among a plurality of output taps having delay times that differ from one another; a second delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first phase detector, receiving the frequency-divided clock signal output from said frequency-dividing circuit and a signal output from said second delay line, for detecting a phase difference between the two signals; and a first counter, receiving an output signal from said first phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said first phase detector and for outputting a tap selection signal that changes over the output taps of said first and second delay lines; a second delay-locked loop circuit including: a third delay line, receiving the frequency-divided clock signal output from the frequency dividing circuit, for outputting a signal obtained by delaying the frequency-divided clock signal, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a fourth delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first multiplexer, receiving output signals of said third and fourth delay lines, for outputting a signal in which timings of rising and falling edges of a pulse are decided by rising edges of respective ones of the two output signals, and in which timings of rising and falling edges of a succeeding pulse are decided by falling edges of respective ones the two output signals; a dummy second multiplexer, receiving the output signal of said first multiplexer; a dummy first buffer, receiving an output of said second multiplexer, and having a delay time identical with that of an output buffer; a dummy second buffer, receiving an output of said dummy first buffer, and having a delay time identical with that of said input buffer; a second phase detector, receiving the clock signal output from said input buffer and a signal output from said dummy second buffer, for detecting a phase difference between the two signals; and a second counter, receiving an output signal from said second phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said second phase detector and for outputting a tap selection signal that changes over the output taps of said third and delay lines; and a third multiplexer, receiving the signal output from said first multiplexer as a data-output clock, for selecting and outputting one item of data among a plurality of items of data applied thereto; said second multiplexer having a delay time identical with that of said third multiplexer; said output buffer, receiving a signal output from said third multiplexer, for outputting the signal as output data from an output terminal.

Claim 3

The semiconductor integrated circuit device according to claim 1 , wherein said first multiplexer includes: a first signal generating circuit, which receives the output signal of said third delay line, for outputting a pulse signal of a predetermined pulse width at positive- and negative-going transitions of the output signal of said third delay line; second signal generating circuit, which receives the output signal of said fourth delay line, for outputting a pulse signal of a predetermined pulse width at positive- and negative-going transitions of the output signal of said fourth delay line; and first and second transistors of mutually opposite conductivity types connected serially between a high-potential power supply and a low-potential power supply for producing an output signal from a connection node of the first and second transistors; wherein a signal obtained by inverting an output signal of said first signal generating circuit is supplied to a control terminal of said first transistor; and a signal obtained by delaying an output signal of said second signal generating circuit is supplied to a control terminal of said second transistor.

Claim 4

The semiconductor integrated circuit device according to claim 1 , wherein said first delay line includes: a first coarse delay line; a first fine delay line, which receives an output signal of said first coarse delay line; a second fine delay line, which receives a signal obtained by inverting the output signal of said first coarse delay line by an inverter; and a fourth multiplexer, which receives output signals of said first fine delay line and said second fine delay line, for synthesizing a single-ended signal; and wherein said second delay line includes: a second coarse delay line; a third fine delay line, which receives an output signal of said second coarse delay line; a fourth fine delay line, which receives a signal obtained by inverting the output signal of said second coarse delay line by an inverter; and a fifth multiplexer, which receives output signals of said third fine delay line and said fourth fine delay line, for synthesizing a single-ended signal.

Claim 5

The semiconductor integrated circuit device according to claim 1 , wherein said third delay line includes: a third coarse delay line; a fifth fine delay line, which receives an output signal of said third coarse delay line; and a sixth fine delay line, which receives a signal obtained by inverting the output signal of said third coarse delay line by an inverter; wherein said fourth delay line includes: a fourth coarse delay line; a seventh fine delay line, which receives an output signal of said fourth coarse delay line; and an eighth fine delay line, which receives a signal obtained by inverting the output signal of said fourth coarse delay line by an inverter; and wherein said first multiplexer, which receives first to fourth delayed signals output from said fifth to eighth fine delay lines, respectively, outputs a signal of which timings of rising and falling edges thereof are decided by rising edges of respective ones of the first and fourth delayed signals, and outputs a signal of which timings of rising and falling edges thereof are decided by rising edges of respective ones of the second and third delayed signals.

Claim 6

The semiconductor integrated circuit device according to claim 1 , further comprising a first aligner, which receives the signal output from said first delay line as a latch timing signal, for latching the tap selection signal output from said first counter and supplying the latched signal to said first and second delay lines.

Claim 7

The semiconductor integrated circuit device according to claim 1 , further comprising a second aligner, which receives the output signal of said first multiplexer as a latch timing signal, for latching the tap selection signal output from said second counter and supplying the latched signal to said third and fourth delay lines.

Claim 8

The semiconductor integrated circuit device according to claim 1 , further comprising a first changeover switch for selecting either the clock signal from said input buffer or the frequency-divided clock from said frequency dividing circuit and supplying the selected signal to said first delay line and said first phase detector.

Claim 9

The semiconductor integrated circuit device according to claim 1 , further comprising: a second input buffer for generating a second clock signal that is a complementary signal of the clock signal output from said input buffer; a second frequency dividing circuit for performing frequency division of the clock signal from said second input buffer and outputting a frequency-divided clock; and a second changeover switch for selecting either the clock signal from said second input buffer or the frequency-divided clock from said second frequency dividing circuit and supplying the selected signal to said fourth delay line.

Claim 10

The semiconductor integrated circuit device according to claim 1 , wherein said first phase detector detects phase lag/lead of the frequency-divided clock using the output signal of said second delay line as a reference; and wherein said second phase detector detects phase lag/lead of the clock signal, which is output from said input buffer, using the signal output from said dummy second buffer as a reference.

Claim 11

The semiconductor integrated circuit device according to claim 1 , wherein said frequency dividing circuit is a divide-by-two frequency dividing circuit for outputting a signal having a frequency obtained by halving the frequency of the signal input thereto.

Claim 12

A semiconductor integrated circuit device, comprising: an input buffer for receiving a clock signal applied thereto; a first delay-locked loop circuit including: a first delay line, receiving the clock signal output from said input buffer, for outputting a signal, obtained by delaying the clock signal from said input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a second delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first phase detector, receiving the clock signal output from said input buffer and the signal output from said second delay line, for detecting a phase difference between the two signals; a first counter, receiving an output signal from said first phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said first phase detector and for outputting a tap selection signal that changes over the output taps of said first and second delay lines; and a first aligner, receiving the signal output from said first delay line as a latch timing signal, for latching the tap selection signal output from said first counter and supplying the latched signal to said first and second delay lines; a second delay-locked loop circuit including: a third delay line, receiving the clock signal output from said first input buffer, for outputting a signal obtained by delaying the clock signal from said input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a fourth delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first multiplexer, receiving two output signals of said third and fourth delay lines, for outputting a signal in which timings of rising and falling edges of a pulse are decided by rising edges of respective ones of the two output signals, and in which timings of rising and falling edges of a succeeding pulse are decided by falling edges of respective ones the two output signals; a dummy second multiplexer, receiving the output signal of said first multiplexer; a dummy first buffer, receiving an output signal of said second multiplexer and having a delay time identical with that of an output buffer; a dummy second buffer, receiving an output signal of said dummy first buffer and having a delay time identical with that of said input buffer; a second phase detector, receiving the clock signal output from said input buffer and a signal output from said dummy second buffer, for detecting a phase difference between the two signals; a second counter, receiving an output signal from said second phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said second phase detector and for outputting a tap selection signal that changes over the output taps of said third and delay lines; and a second aligner, receiving the output signal of said first multiplexer as a latch timing signal, for latching the tap selection signal that is output from said second counter and supplying this signal to said third and fourth delay lines; and a third multiplexer, receiving the signal output from said first multiplexer as a data-output clock, for selecting and outputting one item of data among a plurality of items of data applied thereto; said second multiplexer having a delay time identical with that of said third multiplexer; said output buffer, receiving a signal output from said third multiplexer, outputting the signal as output data from an output terminal.

Claim 13

A semiconductor integrated circuit device, comprising: an input buffer for receiving a clock signal applied thereto; a first delay-locked loop circuit including: a first delay line, receiving the clock signal output from said input buffer, for outputting a signal, obtained by delaying the clock signal from said input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a second delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first phase detector, receiving the clock signal output from said input buffer and the signal output from said second delay line, for detecting a phase difference between the two signals; a first counter, receiving an output signal from said first phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said first phase detector and for outputting a tap selection signal that changes over the output taps of said first and second delay lines; and a first aligner, receiving the signal output from said first delay line as a latch timing signal, for latching the tap selection signal output from said first counter and supplying the latched signal to said first and second delay lines; a second delay-locked loop circuit including: a third delay line, receiving the clock signal output from said first input buffer, for outputting a signal obtained by delaying the clock signal from said input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a fourth delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first multiplexer, receiving two output signals of said third and fourth delay lines, for outputting a signal in which timings of rising and falling edges of a pulse are decided by rising edges of respective ones of the two output signals, and in which timings of rising and falling edges of a succeeding pulse are decided by falling edges of respective ones the two output signals; a dummy second multiplexer, receiving the output signal of said first multiplexer; a dummy first buffer, receiving an output signal of said second multiplexer and having a delay time identical with that of an output buffer; a dummy second buffer, receiving an output signal of said dummy first buffer and having a delay time identical with that of said input buffer; a second phase detector, receiving the clock signal output from said input buffer and a signal output from said dummy second buffer, for detecting a phase difference between the two signals; a second counter, receiving an output signal from said second phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said second phase detector and for outputting a tap selection signal that changes over the output taps of said third and delay lines; and a second aligner, receiving the output signal of said first multiplexer as a latch timing signal, for latching the tap selection signal that is output from said second counter and supplying this signal to said third and fourth delay lines; and a third multiplexer, receiving the signal output from said first multiplexer as a data-output clock, for selecting and outputting one item of data among a plurality of items of data applied thereto; said second multiplexer having a delay time identical with that of said third multiplexer; said output buffer, receiving a signal output from said third multiplexer, outputting the signal as output data from an output terminal.

Claim 14

The semiconductor integrated circuit device according to claim 11 , wherein said first phase detector detects phase lag/lead of the clock signal, which is output from said input buffer, using the output signal of said second delay line as a reference; and wherein said second phase detector detects phase lag/lead of the clock signal, which is output from said input buffer, using the signal output from said dummy second buffer as a reference.

Claim 15

The semiconductor integrated circuit device according to claim 11 , wherein said first multiplexer includes: a first signal generating circuit, which receives the output signal of said third delay line, for outputting a pulse signal of a predetermined pulse width at positive- and negative-going transitions of the output signal of said third delay line; a second signal generating circuit, which receives the output signal of said fourth delay line, for outputting a pulse signal of a predetermined pulse width at positive- and negative-going transitions of the output signal of said fourth delay line; and first and second transistors of mutually opposite conductivity types connected serially between a high-potential power supply and a low-potential power supply for producing an output signal from a connection node of the first and second transistors; wherein a signal obtained by inverting an output signal of said first signal generating circuit is supplied to a control terminal of said first transistor; and a signal obtained by delaying an output signal of said second signal generating circuit is supplied to a control terminal of said second transistor.

Claim 16

The semiconductor integrated circuit device according to claim 11 , wherein said first delay line includes: a first coarse delay line; a first fine delay line, which receives an output signal of said first coarse delay line; a second fine delay line, which receives a signal obtained by inverting the output signal of said first coarse delay line by an inverter; and a fourth multiplexer, which receives output signals of said first fine delay line and said second fine delay line, for synthesizing a single-ended signal; and wherein said second delay line includes: a second coarse delay line; a third fine delay line, which receives an output signal of said second coarse delay line; a fourth fine delay line, which receives a signal obtained by inverting the output signal of said second coarse delay line by an inverter; and a fifth multiplexer, which receives output signals of said third fine delay line and said fourth fine delay line, for synthesizing a single-ended signal.

Claim 17

The semiconductor integrated circuit device according to claim 11 , wherein said third delay line includes: a third coarse delay line; a fifth fine delay line, which receives an output signal of said third coarse delay line; and a sixth fine delay line, which receives a signal obtained by inverting the output signal of said third coarse delay line by an inverter; wherein said fourth delay line includes: a fourth coarse delay line; a seventh fine delay line, which receives an output signal of said fourth coarse delay line; and an eighth fine delay line, which receives a signal obtained by inverting the output signal of said fourth coarse delay line by an inverter; and wherein said first multiplexer, which receives first to fourth delayed signals output from said fifth to eighth fine delay lines, respectively, outputs a signal of which timings of rising and falling edges thereof are decided by rising edges of respective ones of the first and fourth delayed signals, and outputs a signal of which timings of rising and falling edges thereof are decided by rising edges of respective ones of the second and third delayed signals.

Claim 18

A semiconductor integrated circuit device, comprising: an input buffer for receiving a clock signal applied thereto; a delay-locked loop circuit including: a delay line, receiving the clock signal output from said input buffer, for outputting a signal obtained by delaying the clock signal from said input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first multiplexer, receiving the output signal of said delay line; a dummy first buffer, receiving an output signal of said first multiplexer and having a delay time identical with that of an output buffer; a dummy second buffer, receiving an output signal of first buffer and having a delay time identical with that of said input buffer; a phase detector, receiving the clock signal output from said input buffer and an output signal of said dummy second buffer, for detecting a phase difference between the two signals; a counter, receiving an output signal from said phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said phase detector and for outputting a tap selection signal that changes over the output tap of said delay line; and an aligner, receiving the output signal of said delay line as a latch timing signal, for latching the tap selection signal output from said counter and supplying the latched signal to said delay line; and a second multiplexer, receiving the signal output from said delay line as a data-output clock, for selecting and outputting one item of data among a plurality of items of data applied thereto; said first multiplexer having a delay time identical with that of said second multiplexer; said output buffer, receiving a signal output from said second multiplexer, outputting the signal as output data from an output terminal.

Claim 19

A semiconductor integrated circuit device, comprising: an input buffer for receiving a clock signal applied thereto; a delay-locked loop circuit including: a delay line, receiving the clock signal output from said input buffer, for outputting a signal obtained by delaying the clock signal from said input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first multiplexer, receiving the output signal of said delay line; a dummy first buffer, receiving an output signal of said first multiplexer and having a delay time identical with that of an output buffer; a dummy second buffer, receiving an output signal of first buffer and having a delay time identical with that of said input buffer; a phase detector, receiving the clock signal output from said input buffer and an output signal of said dummy second buffer, for detecting a phase difference between the two signals; a counter, receiving an output signal from said phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said phase detector and for outputting a tap selection signal that changes over the output tap of said delay line; and an aligner, receiving the output signal of said delay line as a latch timing signal, for latching the tap selection signal output from said counter and supplying the latched signal to said delay line; and a second multiplexer, receiving the signal output from said delay line as a data-output clock, for selecting and outputting one item of data among a plurality of items of data applied thereto; said first multiplexer having a delay time identical with that of said second multiplexer; said output buffer, receiving a signal output from said second multiplexer, outputting the signal as output data from an output terminal.

Claim 20

The semiconductor integrated circuit device according to claim 16 , wherein said phase detector detects phase lag/lead of the clock signal, which is output from said input buffer, using the signal output from said dummy second buffer as a reference.

Claim 21

A delay-locked loop device comprising: a first delay-locked loop for adjusting delay times of serially connected first and second delay lines in such a manner that a signal obtained by delaying an input signal by the first and second delay lines is in phase with the input signal, thereby outputting, from the first delay line, a signal that is the result of delaying the input signal by one half cycle of the input signal, said first delay-locked loop including: a frequency dividing circuit for performing frequency division of the input signal, an output signal from said frequency dividing circuit being delayed by said first and second delay lines; and first delay adjustment means for outputting a control signal for adjusting the delay times of said first and second delay lines in such a manner that the output signal of said frequency dividing circuit and an output signal of said second delay line are in phase; and a second delay-locked loop for generating a data-output clock signal based upon the input signal and supplying the data-output clock to a multiplexer that selectively outputs multiple items of data, said second delay-locked loop including: a third delay line, receiving the output signal of said frequency dividing circuit, for outputting a first signal by delaying this output signal; a fourth delay line, receiving an output signal of said first delay-locked loop device, for outputting a second signal by delaying this output signal; a circuit, receiving the first and second signals from said third and fourth delay lines, respectively, for outputting, as the data-output clock, a signal in which timings of rising and falling edges of a pulse are decided by rising edges of respective ones of the first and second signals, and in which timings of rising and falling edges of a succeeding pulse are decided by falling edges of respective ones of the first and second signals; and second delay adjusting means for outputting a control signal for adjusting delay times of said third and fourth delay lines in such a manner that a signal obtained by delaying the data-output clock by at least a delay time of said multiplexer is in phase with the input signal.

Claim 22

A delay-locked loop device comprising: a first delay-locked loop for adjusting delay times of serially connected first and second delay lines in such a manner that a signal obtained by delaying an input signal by the first and second delay lines is in phase with the input signal, thereby outputting, from the first delay line, a signal that is the result of delaying the input signal by one half cycle of the input signal, said first delay-locked loop including: a frequency dividing circuit for performing frequency division of the input signal, an output signal from said frequency dividing circuit being delayed by said first and second delay lines; and first delay adjustment means for outputting a control signal for adjusting the delay times of said first and second delay lines in such a manner that the output signal of said frequency dividing circuit and an output signal of said second delay line are in phase; and a second delay-locked loop for generating a data-output clock signal based upon the input signal and supplying the data-output clock to a multiplexer that selectively outputs multiple items of data, said second delay-locked loop including: a third delay line, receiving the output signal of said frequency dividing circuit, for outputting a first signal by delaying this output signal; a fourth delay line, receiving an output signal of said first delay-locked loop device, for outputting a second signal by delaying this output signal; a circuit, receiving the first and second signals from said third and fourth delay lines, respectively, for outputting, as the data-output clock, a signal in which timings of rising and falling edges of a pulse are decided by rising edges of respective ones of the first and second signals, and in which timings of rising and falling edges of a succeeding pulse are decided by falling edges of respective ones of the first and second signals; and second delay adjusting means for outputting a control signal for adjusting delay times of said third and fourth delay lines in such a manner that a signal obtained by delaying the data-output clock by at least a delay time of said multiplexer is in phase with the input signal.

Claim 23

The delay-locked loop device according to claim 18 , further comprising a second latch circuit for supplying the control signal from said second delay adjusting means to said third and fourth delay lines upon latching the control signal from said second delay adjustment means by the data-output clock.

Claim 24

The delay-locked loop device according to claim 18 , further comprising a first latch circuit for supplying the control signal from said first delay adjusting means to said first and second delay lines upon latching the control signal from said first delay adjustment means by the output signal of said first delay line.

Claim 25

A delay-locked loop device for adjusting delay times of serially connected first and second delay lines in such a manner that a signal obtained by delaying an input signal by the first and second delay lines is in phase with the input signal, thereby outputting, from the first delay line, a signal that is the result of delaying the input signal by one half cycle of the input signal, comprising: a frequency dividing circuit for performing frequency division of the input signal, an output signal from said frequency dividing circuit being delayed by said first and second delay lines; first delay adjustment means for outputting a control signal for adjusting the delay times of said first and second delay lines in such a manner that the output signal of said frequency dividing circuit and an output signal of said second delay line are in phase; and a first latch circuit for supplying the control signal from said first delay adjusting means to said first and second delay lines upon latching the control signal from said first delay adjustment means by the output signal of said first delay line.

Claim 26

A delay-locked loop device for adjusting delay times of serially connected first and second delay lines in such a manner that a signal obtained by delaying an input signal by the first and second delay lines is in phase with the input signal, thereby outputting, from the first delay line, a signal that is the result of delaying the input signal by one half cycle of the input signal, comprising: a frequency dividing circuit for performing frequency division of the input signal, an output signal from said frequency dividing circuit being delayed by said first and second delay lines; first delay adjustment means for outputting a control signal for adjusting the delay times of said first and second delay lines in such a manner that the output signal of said frequency dividing circuit and an output signal of said second delay line are in phase; and a first latch circuit for supplying the control signal from said first delay adjusting means to said first and second delay lines upon latching the control signal from said first delay adjustment means by the output signal of said first delay line.

Claim 27

A delay-locked loop device comprising a first delay-locked loop and a second delay-locked loop; said first delay-locked loop including: a first delay line receiving a clock signal obtained as a result of dividing a frequency of a clock signal output from an input buffer, using a frequency divider, for outputting a signal obtained by delaying the frequency-divided clock signal, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a second delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first phase detector, receiving the frequency-divided clock signal and a signal output from said second delay line, for detecting a phase difference between the two signals; and a first counter, receiving an output signal from said first phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said first phase detector and for outputting a tap selection signal that changes over the output taps of said first and second delay lines; and said second delay-locked loop including: a third delay line, receiving the frequency-divided clock signal output from said frequency dividing circuit, for outputting a signal obtained by delaying the frequency-divided clock signal, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a fourth delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first multiplexer, receiving output signals of said third and fourth delay lines, for outputting a signal in which timings of rising and falling edges of a pulse are decided by rising edges of respective ones of the two output signals, and in which timings of rising and falling edges of a succeeding pulse are decided by falling edges of respective ones the two output signals; delay means for delaying the signal output from said first multiplexer a predetermined length of time; a second phase detector, receiving the clock signal output from said input buffer and an output signal of said delay means, for detecting a phase difference between the two signals; and a second counter, receiving an output signal from said second phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said second phase detector and for outputting a tap selection signal that changes over the output taps of said third and fourth delay lines.

Claim 28

A delay-locked loop device comprising a first delay-locked loop and a second delay-locked loop; said first delay-locked loop including: a first delay line receiving a clock signal obtained as a result of dividing a frequency of a clock signal output from an input buffer, using a frequency divider, for outputting a signal obtained by delaying the frequency-divided clock signal, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a second delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first phase detector, receiving the frequency-divided clock signal and a signal output from said second delay line, for detecting a phase difference between the two signals; and a first counter, receiving an output signal from said first phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said first phase detector and for outputting a tap selection signal that changes over the output taps of said first and second delay lines; and said second delay-locked loop including: a third delay line, receiving the frequency-divided clock signal output from said frequency dividing circuit, for outputting a signal obtained by delaying the frequency-divided clock signal, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a fourth delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first multiplexer, receiving output signals of said third and fourth delay lines, for outputting a signal in which timings of rising and falling edges of a pulse are decided by rising edges of respective ones of the two output signals, and in which timings of rising and falling edges of a succeeding pulse are decided by falling edges of respective ones the two output signals; delay means for delaying the signal output from said first multiplexer a predetermined length of time; a second phase detector, receiving the clock signal output from said input buffer and an output signal of said delay means, for detecting a phase difference between the two signals; and a second counter, receiving an output signal from said second phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said second phase detector and for outputting a tap selection signal that changes over the output taps of said third and fourth delay lines.

Claim 29

The delay-locked loop device according to claim 22 , wherein said first multiplexer includes: a first signal generating circuit, receiving the output signal of said third delay line, for outputting a pulse signal of a predetermined pulse width at positive- and negative-going transitions of the output signal of said third delay line; a second signal generating circuit, receiving the output signal of said fourth delay line, for outputting a pulse signal of a predetermined pulse width at positive- and negative-going transitions of the output signal of said fourth delay line; and first and second transistors of mutually opposite conductivity types connected serially between a high-potential power supply and a low-potential power supply for producing an output signal from a connection node of first and second transistors; wherein a signal obtained by inverting an output signal of said first signal generating circuit is supplied to a control terminal of said first transistor; and wherein a signal obtained by delaying an output signal of said second signal generating circuit is supplied to a control terminal of said second transistor.

Claim 30

The delay-locked loop device according to claim 22 , wherein said first delay line includes: a first coarse delay line; a first fine delay line, receiving an output signal of said first coarse delay line; a second fine delay line, receiving a signal obtained by inverting the output signal of said first coarse delay line by an inverter; and a fourth multiplexer, receiving output signals of said first fine delay line and said second fine delay line, for synthesizing a single-ended signal; and wherein said second delay line includes: a second coarse delay line; a third fine delay line, receiving an output signal of said second coarse delay line; a fourth fine delay line, receiving a signal obtained by inverting the output signal of said second coarse delay line by an inverter; and a fifth multiplexer, receiving output signals of said third fine delay line and said fourth fine delay line, for synthesizing a single-ended signal.

Claim 31

The delay-locked loop device according to claim 22 , wherein said third delay line includes: a third coarse delay line; a fifth fine delay line, receiving an output signal of said third coarse delay line; and a sixth fine delay line, receiving a signal obtained by inverting the output signal of said third coarse delay line by an inverter; wherein said fourth delay line includes: a fourth coarse delay line; a seventh fine delay line, receiving an output signal of said fourth coarse delay line; and a eighth fine delay line, receiving a signal obtained by inverting the output signal of said fourth coarse delay line by an inverter; and wherein said first multiplexer, receiving first to fourth delayed signals output from said fifth to eighth fine delay lines, respectively, outputs a signal of which timings of rising and falling edges thereof are decided by rising edges of respective ones of the first and fourth delayed signals, and outputs a signal of which timings of rising and falling edges thereof are decided by rising edges of respective ones of the second and third delayed signals.

Claim 32

The delay-locked loop device according to claim 22 , further comprising a first aligner, which receives the signal output from said first delay line as a latch timing signal, for latching the tap selection signal that is output from said first counter and supplying this signal to said first and second delay lines.

Claim 33

The delay-locked loop device according to claim 22 , further comprising a second aligner, which receives the output signal of said first multiplexer as a latch timing signal, for latching the tap selection signal that is output from said second counter and supplying this signal to said third and fourth delay lines.

Claim 34

The delay-locked loop device according to claim 22 , wherein said frequency dividing circuit is a divide-by-two frequency dividing circuit for outputting a signal having a frequency obtained by halving the frequency of the signal input thereto.

Claim 35

A delay-locked loop device comprising a first delay-locked loop and a second delay-locked loop; said first delay-locked loop including: a first delay line, receiving a clock signal output from an input buffer having the clock signal applied thereto, for outputting a signal obtained by delaying the clock signal from the input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a second delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first phase detector, receiving the output clock signal of the input buffer and a signal output from said second delay line, for detecting a phase difference between the two signals; a first counter, receiving an output signal from said first phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said first phase detector and for outputting a tap selection signal that changes over the output taps of said first and second delay lines; and a first aligner, receiving the output signal of said first delay line as a latch timing signal, for latching the tap selection signal output from said first counter, and supplying the latched signal to said first and second delay lines; and said second delay-locked loop including: a third delay line, receiving the clock signal output from the input buffer, for outputting a signal obtained by delaying the clock signal from the input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a fourth delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first multiplexer, receiving output signals of said third and fourth delay lines, for outputting a signal in which timings of rising and falling edges of a pulse are decided by rising edges of respective ones of the two output signals, and in which timings of rising and falling edges of a succeeding pulse are decided by falling edges of respective ones the two output signals; delay means for delaying the signal output from said first multiplexer a predetermined length of time; a second phase detector, receiving the clock signal output from said input buffer and an output signal of said delay means, for detecting a phase difference between the two signals; a second counter, receiving an output signal from said second phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said second phase detector and for outputting a tap selection signal that changes over the output taps of said third and fourth delay lines; and a second aligner, receiving the output signal of said first multiplexer as a latch timing signal, for latching the tap selection signal output from said second counter, and supplying this signal to said third and fourth delay lines.

Claim 36

A delay-locked loop device comprising a first delay-locked loop and a second delay-locked loop; said first delay-locked loop including: a first delay line, receiving a clock signal output from an input buffer having the clock signal applied thereto, for outputting a signal obtained by delaying the clock signal from the input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a second delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first phase detector, receiving the output clock signal of the input buffer and a signal output from said second delay line, for detecting a phase difference between the two signals; a first counter, receiving an output signal from said first phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said first phase detector and for outputting a tap selection signal that changes over the output taps of said first and second delay lines; and a first aligner, receiving the output signal of said first delay line as a latch timing signal, for latching the tap selection signal output from said first counter, and supplying the latched signal to said first and second delay lines; and said second delay-locked loop including: a third delay line, receiving the clock signal output from the input buffer, for outputting a signal obtained by delaying the clock signal from the input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a fourth delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another; a first multiplexer, receiving output signals of said third and fourth delay lines, for outputting a signal in which timings of rising and falling edges of a pulse are decided by rising edges of respective ones of the two output signals, and in which timings of rising and falling edges of a succeeding pulse are decided by falling edges of respective ones the two output signals; delay means for delaying the signal output from said first multiplexer a predetermined length of time; a second phase detector, receiving the clock signal output from said input buffer and an output signal of said delay means, for detecting a phase difference between the two signals; a second counter, receiving an output signal from said second phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said second phase detector and for outputting a tap selection signal that changes over the output taps of said third and fourth delay lines; and a second aligner, receiving the output signal of said first multiplexer as a latch timing signal, for latching the tap selection signal output from said second counter, and supplying this signal to said third and fourth delay lines.

Claim 37

The delay-locked loop device according to claim 29 , wherein said first multiplexer includes: a first signal generating circuit, receiving the output signal of said third delay line, for outputting a pulse signal of a predetermined pulse width at positive- and negative-going transitions of the output signal of said third delay line; a second signal generating circuit, receiving the output signal of said fourth delay line, for outputting a pulse signal of a predetermined pulse width at positive- and negative-going transitions of the output signal of said fourth delay line; and first and second transistors of mutually opposite conductivity types connected serially between a high-potential power supply and a low-potential power supply for producing an output signal from a connection node of first and second transistors; wherein a signal obtained by inverting an output signal of said first signal generating circuit is supplied to a control terminal of said first transistor; and wherein a signal obtained by delaying an output signal of said second signal generating circuit is supplied to a control terminal of said second transistor.

Claim 38

The delay-locked loop device according to claim 29 , wherein said first delay line includes: a first coarse delay line; a first fine delay line, receiving an output signal of said first coarse delay line; a second fine delay line, receiving a signal obtained by inverting the output signal of said first coarse delay line by an inverter; and a fourth multiplexer, receiving output signals of said first fine delay line and said second fine delay line, for synthesizing a single-ended signal; and wherein said second delay line includes: a second coarse delay line; a third fine delay line, receiving an output signal of said second coarse delay line; a fourth fine delay line, receiving a signal obtained by inverting the output signal of said second coarse delay line by an inverter; and a fifth multiplexer, receiving output signals of said third fine delay line and said fourth fine delay line, for synthesizing a single-ended signal.

Claim 39

The delay-locked loop device according to claim 29 , wherein said third delay line includes: a third coarse delay line; a fifth fine delay line, receiving an output signal of said third coarse delay line; and a sixth fine delay line, receiving a signal obtained by inverting the output signal of said third coarse delay line by an inverter; wherein said fourth delay line includes: a fourth coarse delay line; a seventh fine delay line, receiving an output signal of said fourth coarse delay line; and a eighth fine delay line, receiving a signal obtained by inverting the output signal of said fourth coarse delay line by an inverter; and wherein said first multiplexer, receiving first to fourth delayed signals output from said fifth to eight fine delay lines, respectively, outputs a signal of which timings of rising and falling edges thereof are decided by rising edges of respective ones of the first and fourth delayed signals, and outputs a signal of which timings of rising and falling edges thereof are decided by rising edges of respective ones of the second and third delayed signals.

Claim 40

A delay-locked loop device comprising: a delay line, receiving a clock signal that is output from an input buffer having the clock signal applied thereto, for outputting a signal obtained by delaying the clock signal from said input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another; delay means for delaying the signal output from said delay line a predetermined length of time; a phase detector, receiving the clock signal output from said input buffer and an output signal of said delay means, for detecting a phase difference between the two signals; and a counter, receiving an output signal from said phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said phase detector and for outputting a tap selection signal that changes over the output tap of said delay line; and an aligner, receiving the signal output from said delay line as a latch timing signal, for latching the tap selection signal that is output from said first counter and supplying this signal to said delay line.

Claim 41

A delay-locked loop device comprising: a delay line, receiving a clock signal that is output from an input buffer having the clock signal applied thereto, for outputting a signal obtained by delaying the clock signal from said input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another; delay means for delaying the signal output from said delay line a predetermined length of time; a phase detector, receiving the clock signal output from said input buffer and an output signal of said delay means, for detecting a phase difference between the two signals; and a counter, receiving an output signal from said phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said phase detector and for outputting a tap selection signal that changes over the output tap of said delay line; and an aligner, receiving the signal output from said delay line as a latch timing signal, for latching the tap selection signal that is output from said first counter and supplying this signal to said delay line.