Synchronous delay circuit and semiconductor integrated circuit apparatus

Claim 2

A synchronous delay circuit apparatus comprising: (a) a plurality of sets of synchronous delay circuits, each set including a first delay circuit chain for delay measurement, along which input clock signals propagate, and a second delay circuit chain, connected to said first delay circuit chain, a difference being measured by said first delay circuit chain, said difference being between the delay time of a preset circuit or path for propagating and outputting clocks and the period of input clocks, said second delay circuit chain reproducing and outputting the measured time difference; (b) wherein at least one of said sets of the synchronous delay circuits, in combination with at least one delay circuit, has a measured delay quantity different from that of the other or others of the synchronous delay circuits, without causing discontinuity in clocks output from said synchronous delay circuits to said preset circuit or path even when the relative relation in the magnitudes between the delay time of the preset circuit or path and the period of said input clock is changed.

Claim 3

A synchronous delay circuit apparatus comprising: (a) a plurality of sets of synchronous delay circuits, each set including a first delay circuit chain for delay measurement, along which input clock signals propagate, and a second delay circuit chain for allowing the input clock signals to propagate through a length corresponding to a length of propagation of the input clock signals through said first delay circuit chain; and (b) delay detection circuits each controlling operation of one said first delay circuit chain, said delay detection circuits each detecting a propagation delay time required for propagating clock signals from an input node to a preset output node of a preset clock propagation path, each said delay detection circuit outputting a control signal for controlling said one first delay circuit chain to halt the propagation of the input clock signals based upon, at least in part, said propagation delay time; (c) wherein delay is introduced by at least one delay circuit to an input of at least one of said delay detection circuits to differentiate at least one delay time as detected in said at least one of said delay detection circuits from delay times detected by the other delay detection circuits to differentiate at least one detected period quantity detected in the at least one first delay circuit chain controlled by said at least one of said delay detection circuits from a detected period quantity detected in each said first delay circuit chain controlled by each of said other delay detection circuits, so that, even when the propagation delay time in said preset clock propagation path becomes longer or shorter than a clock period of the input clock signals, no discontinuity is produced in clock signals supplied from one of said sets of synchronous delay circuits to said clock propagation path.

Claim 4

A synchronous delay circuit apparatus comprising: (a) a plurality of sets of synchronous delay circuits, each set including a first delay circuit chain for delay measurement, along which input clock signals propagate, and a second delay circuit chain for allowing the input clock signals to propagate through a length corresponding to a length of propagation of the input clock signals through said first delay circuit chain; and (b) delay detection circuits each controlling operation of one said first delay circuit chain, said delay detection circuits each detecting a propagation delay time required for propagating clock signals from an input node to a preset output node of a preset clock propagation path, each said delay detection circuit outputting a control signal for controlling said one first delay circuit chain to halt the propagation of the input clock signals based upon, at least in part, said propagation delay time; (c) wherein delay is introduced by at least one delay circuit to an input of at least one of said delay detection circuits to differentiate at least one delay time as detected in said at least one of said delay detection circuits from delay times detected by the other delay detection circuits to differentiate at least one detected period quantity detected in the at least one first delay circuit chain controlled by said at least one of said delay detection circuits from a detected period quantity detected in each said first delay circuit chain controlled by each of said other delay detection circuits, so that, even when the propagation delay time in said preset clock propagation path becomes longer or shorter than a clock period of the input clock signals, no discontinuity is produced in clock signals supplied from one of said sets of synchronous delay circuits to said clock propagation path.

Claim 5

A synchronous delay circuit apparatus comprising: (a) two sets of synchronous delay circuits, each set including a first delay circuit chain for period measurement for propagation of pulses or pulse edges of input clock signals and a second delay circuit chain, said second delay circuit chain allowing pulses or pulse edges of said input clock signals to propagate through a length corresponding to a length traversed by said pulses or pulse edges of said input clock signals through said first delay circuit chain; and (b) two delay detection circuits each controlling operation of one said first delay circuit chain, each delay detection circuit detecting a propagation delay time in propagating clock signals from an input node to a preset output node of a preset clock propagation path and outputting a control signal for controlling said one first delay circuit chain to cease the propagation of the pulses or pulse edges of the input clock signals based upon, at least in part, said propagation delay time; (c) wherein delay is introduced by at least one delay circuit to an input of at least one of said delay detection circuits to differentiate a delay time as detected in one of said delay detection circuits from a delay time detected by the other of the delay detection circuits to differentiate a detected period quantity detected in one said first delay circuit chain controlled by said one of said delay detection circuits from a detected period quantity detected in another said first delay circuit chain controlled by said other of the delay detection circuits, so that, even when the propagation delay time in said preset clock propagation path becomes longer or shorter than a clock period of the input clock signals, no discontinuity is produced in clock signals supplied from one of said sets of synchronous delay circuits to said clock propagation path.

Claim 6

A synchronous delay circuit apparatus comprising: (a) two sets of synchronous delay circuits, each set including a first delay circuit chain for period measurement for propagation of pulses or pulse edges of input clock signals and a second delay circuit chain, said second delay circuit chain allowing pulses or pulse edges of said input clock signals to propagate through a length corresponding to a length traversed by said pulses or pulse edges of said input clock signals through said first delay circuit chain; and (b) two delay detection circuits each controlling operation of one said first delay circuit chain, each delay detection circuit detecting a propagation delay time in propagating clock signals from an input node to a preset output node of a preset clock propagation path and outputting a control signal for controlling said one first delay circuit chain to cease the propagation of the pulses or pulse edges of the input clock signals based upon, at least in part, said propagation delay time; (c) wherein delay is introduced by at least one delay circuit to an input of at least one of said delay detection circuits to differentiate a delay time as detected in one of said delay detection circuits from a delay time detected by the other of the delay detection circuits to differentiate a detected period quantity detected in one said first delay circuit chain controlled by said one of said delay detection circuits from a detected period quantity detected in another said first delay circuit chain controlled by said other of the delay detection circuits, so that, even when the propagation delay time in said preset clock propagation path becomes longer or shorter than a clock period of the input clock signals, no discontinuity is produced in clock signals supplied from one of said sets of synchronous delay circuits to said clock propagation path.

Claim 7

The synchronous delay circuit as defined in claim 2 wherein delay circuit elements forming said first delay circuit chain are clocked inverters on-off control led by said control signal.

Claim 8

The synchronous delay circuit as defined in claim 3 wherein delay circuit elements forming said first delay circuit chain a are clocked inverters on-off controlled by said control signal.

Claim 9

The synchronous delay circuit as defined in claim 2 wherein there is provided a switching over unit for switching over between an output of each second delay circuit chain of each synchronous delay circuit, and said input clock signals, an output of said switching over unit being connected to an input node of said preset clock propagation path.

Claim 10

The synchronous delay circuit as defined in claim 3 wherein there is provided a switching over unit for switching over between an output of each second delay circuit chain of each synchronous delay circuit, and said input clock signals, an output of said switching over unit being connected to an input node of said preset clock propagation path.

Claim 11

The synchronous delay circuit as defined in claim 2 wherein said delay detection circuit comprises a flipflop that is reset responsive to said clock signals reaching said input node of said preset clock propagation path and set responsive to said clock signals reaching said preset output node of said preset clock propagation path.

Claim 12

The synchronous delay circuit as defined in claim 3 wherein said delay detection circuit comprises a flipflop that is reset responsive to said clock signals reaching said input node of said preset clock propagation path and set responsive to said clock signals reaching said preset output node of said preset clock propagation path.

Claim 13

A semiconductor integrated circuit apparatus in which a clock signal supplied to a clock propagation path is controlled using a plurality of sets of synchronous delay circuits, said semiconductor integrated circuit comprising: (a) each set of said plurality of sets of synchronous delay circuits including a first delay circuit chain for period measurement, along which input clock signals propagate, and a second delay circuit chain, allowing the input clock signals to propagate through a length corresponding to a length of propagation of said input clock signals through said first delay circuit chain; and (b) delay detection circuits each controlling operation of one said first delay circuit chain, said delay detection circuits each detecting a propagation delay time required for propagating clock signals from an input node to a preset output node of a preset clock propagation path, each said delay detection circuit outputting a control signal for controlling said one first delay circuit chain to cease the propagation of the input clock signals based upon, at least in part, said propagation delay time; (c) wherein delay (td) is introduced by at least one delay circuit to an input of at least one of said delay detection circuits to differentiate at least one delay time as detected in said at least one of said delay detection circuits from delay times detected by the other delay detection circuits, to differentiate at least one detected period quantity detected in the at least one of said first delay circuit chain controlled by said at least one of said delay detection circuits from a detected period quantity detected in each said first delay circuit chain controlled by each of said other delay detection circuits, so that, even when the relative relation in the magnitudes of the propagation delay time (tCTS) of said preset clock propagation path and a clock period (tCK) of the input clock signals is changed to cause discontinuity in clock signals from a given one of said sets of the synchronous delay circuits, clock signals synchronized with the input clock signals are output from another of the sets of the synchronous delay circuits and routed to said preset clock propagation path.

Claim 14

A semiconductor integrated circuit apparatus in which a clock signal supplied to a clock propagation path is controlled using a plurality of sets of synchronous delay circuits, said semiconductor integrated circuit comprising: (a) each set of said plurality of sets of synchronous delay circuits including a first delay circuit chain for period measurement, along which input clock signals propagate, and a second delay circuit chain, allowing the input clock signals to propagate through a length corresponding to a length of propagation of said input clock signals through said first delay circuit chain; and (b) delay detection circuits each controlling operation of one said first delay circuit chain, said delay detection circuits each detecting a propagation delay time required for propagating clock signals from an input node to a preset output node of a preset clock propagation path, each said delay detection circuit outputting a control signal for controlling said one first delay circuit chain to cease the propagation of the input clock signals based upon, at least in part, said propagation delay time; (c) wherein delay (td) is introduced by at least one delay circuit to an input of at least one of said delay detection circuits to differentiate at least one delay time as detected in said at least one of said delay detection circuits from delay times detected by the other delay detection circuits, to differentiate at least one detected period quantity detected in the at least one of said first delay circuit chain controlled by said at least one of said delay detection circuits from a detected period quantity detected in each said first delay circuit chain controlled by each of said other delay detection circuits, so that, even when the relative relation in the magnitudes of the propagation delay time (tCTS) of said preset clock propagation path and a clock period (tCK) of the input clock signals is changed to cause discontinuity in clock signals from a given one of said sets of the synchronous delay circuits, clock signals synchronized with the input clock signals are output from another of the sets of the synchronous delay circuits and routed to said preset clock propagation path.

Claim 15

A semiconductor integrated circuit apparatus for controlling clock signals supplied to a clock propagation path using synchronous delay circuits, comprising: (a) a first synchronous delay circuit including a first delay circuit chain for period measurement, that allows propagation of input clock signals and a second delay circuit chain, said second delay circuit chain allowing the input clock signals to propagate through a length corresponding to a length traversed by said input clock signals through said first delay circuit chain; and (b) a first delay detection circuit for detecting a propagation delay time (tCTS) in propagating the clock signals from an input node to a preset output node of the clock propagation path and outputting a first control signal for controlling said first delay circuit chain to cease the propagation of the input clock signals for a period of time based upon, at least in part, said propagation delay time; (c) a second synchronous delay circuit including a third delay circuit chain, for period measurement, that allows propagation of input clock signals and a fourth delay circuit chain, said fourth delay circuit chain allowing the input clock signals to propagate through a length corresponding to a length traversed by said input clock signals through said third delay circuit chain; and (d) a second delay detection circuit for detecting the propagation delay time (tCTS) in propagating the clock signals from the input node to the preset output node of the clock propagation path and outputting a second control signal for controlling said third delay circuit chain to cease the propagation of the input clock signals for a period of time based upon, at least in part, said propagation delay time; (e) wherein outputs of said second and fourth delay circuit chains are fed to said input node of said clock propagation path through a switching over unit.

Claim 16

A semiconductor integrated circuit apparatus for controlling clock signals supplied to a clock propagation path using synchronous delay circuits, comprising: (a) a first synchronous delay circuit including a first delay circuit chain for period measurement, that allows propagation of input clock signals and a second delay circuit chain, said second delay circuit chain allowing the input clock signals to propagate through a length corresponding to a length traversed by said input clock signals through said first delay circuit chain; and (b) a first delay detection circuit for detecting a propagation delay time (tCTS) in propagating the clock signals from an input node to a preset output node of the clock propagation path and outputting a first control signal for controlling said first delay circuit chain to cease the propagation of the input clock signals for a period of time based upon, at least in part, said propagation delay time; (c) a second synchronous delay circuit including a third delay circuit chain, for period measurement, that allows propagation of input clock signals and a fourth delay circuit chain, said fourth delay circuit chain allowing the input clock signals to propagate through a length corresponding to a length traversed by said input clock signals through said third delay circuit chain; and (d) a second delay detection circuit for detecting the propagation delay time (tCTS) in propagating the clock signals from the input node to the preset output node of the clock propagation path and outputting a second control signal for controlling said third delay circuit chain to cease the propagation of the input clock signals for a period of time based upon, at least in part, said propagation delay time; (e) wherein outputs of said second and fourth delay circuit chains are fed to said input node of said clock propagation path through a switching over unit.

Claim 17

The semiconductor integrated circuit as defined in claim 11 wherein a first delay circuit having a fixed delay time is provided between said preset output node in said clock propagation path and an input terminal of said second delay detection circuit, and a second delay circuit having said fixed delay time is inserted between an output of said fourth delay circuit chain and an input terminal of said switching over unit.

Claim 18

The semiconductor integrated circuit as defined in claim 11 wherein delay circuit elements forming said first delay circuit chain comprise clocked inverters on-off controlled by said control signal.

Claim 19

The semiconductor integrated circuit as defined in claim 11 wherein said first and second delay detection circuits are flipflops being reset and set by said clock signals reaching said input node of said clock propagation path and said clock signals reaching said preset output node of said clock propagation path.

Claim 20

The semiconductor integrated circuit as defined in claim 11 wherein a delay circuit having a fixed delay time is provided between said input node in said clock propagation path and an input terminal of said second delay detection circuit.