Multiplex synchronous delay circuit

Claim 2

A multiplex synchronous delay circuit comprising: a plurality of synchronous delay circuit means, wherein pulse signals are input into a plurality of gate sections in cascade connection within each of said synchronous delay circuit means, and said pulse signals are transmitted through said gate sections in sequential delays, and said gate sections output in parallel and are synchronized with said pulse signals, and wherein, based on each output in parallel, delay signals output from said plurality of synchronous delay circuit means have a fixed delay time corresponding to said pulse signals, and delay time differentials between said plurality of synchronous delay circuit means are maintained in sequential order; and a multiplex circuit means that inputs each of said delay signals, multiplexes said delay signals, and outputs the result as multiplex delay signals.

Claim 3

A multiplex synchronous delay circuit according to claim 1 wherein each of said synchronous delay circuit means comprises: an input delay adjustment circuit that inputs a signal corresponding to said pulse signal and equally adjusts each of said delay time differentials; a first delay circuit bank made up of a plurality of gate sections in cascade connection that inputs and sequentially delays output of said input delay adjustment circuit and parallel outputs output of each of said gate sections in the order of the gate sections starting from the input side; a control circuit that parallel inputs output of each gate section of said first delay circuit bank, synchronizes with said pulse signal, and parallel outputs each result; a second delay circuit bank made up of a plurality of gate sections in cascade connection arranged in the reverse direction of the signal transmission path of said first delay circuit bank that parallel inputs to each gate section each output of said control circuit in the order of said gate sections from the output side, sequentially delays these inputs, and outputs the result; and an output delay adjustment circuit that inputs output of said second delay circuit bank, equally adjusts each of said delay time differentials, and outputs the result as one of said delay signals.

Claim 4

A multiplex synchronous delay circuit according to claim 2 wherein said second delay circuit bank comprises m rows of delay circuit sub-banks each made up of a plurality of gate sections in cascade connection arranged in the reverse direction of the signal transmission path of said first delay circuit bank, and the (d)th delay circuit sub-bank of said m rows of delay circuit sub-banks includes means for parallel inputting to every (n)th gate section from the output side the output of every (m)th gate section from the (d)th gate section of said control circuit, sequentially delays these inputs, and outputs the result; means for maintaining equal delay time differentials with respect to output of each of these m rows of delay circuit sub-banks and sequentially outputting the result; and means for multiplexing of these outputs and outputting the result to said output delay adjustment circuit.

Claim 5

A multiplex synchronous delay circuit according to claim 3 wherein said second delay circuit bank comprises: m sub-output delay adjustment circuits that input output of each of said m rows of delay circuit sub-banks, equally adjust each of said sub-delay time differentials, and output the result; and a sub-multiplex circuit that inputs outputs of said m sub-output delay adjustment circuits, multiplexes said output, and outputs the result.

Claim 6

A multiplex synchronous delay circuit according to claim 1 wherein each of said synchronous delay circuit means comprises: an input delay adjustment circuit that inputs a signal corresponding to said pulse signal and equally adjusts each of said delay time differentials; a first delay circuit bank made up of a plurality of gate sections in cascade connection and loop connection that inputs and sequentially delays output of said input delay adjustment circuit and parallel outputs output of each of said gate sections in the order of the gate sections from the input side; a control circuit that parallel inputs output of each gate section of said first delay circuit bank, synchronizes with said pulse signal, and parallel outputs each result; a second delay circuit bank made up of a plurality of gate sections in cascade connection and loop connection arranged in the reverse direction of the signal transmission path of said first delay circuit bank that parallel inputs to each gate section each output of said control circuit in the order of the gate sections from the output side, sequentially delays these inputs, and outputs the result; counting means that adds each time a signal corresponding to said pulse signal makes a circuit of the loop within said first delay circuit bank, subtracts each time a signal corresponding to said pulse signal makes a circuit of the loop in said second delay circuit bank, and outputs a signal indicating that the number of circuits completed in said first and second delay circuit banks are equal; a selector circuit that, in accordance with output of said counting means, extracts from output a signal corresponding to said pulse signal circulating within said second delay circuit bank; and an output delay adjustment circuit that inputs output of said selector circuit, equally adjusts each of said delay time differentials, and outputs the result as one of said delay signals.

Claim 7

A multiplex synchronous delay circuit according to claim 5 wherein said counting means comprises: an adder that adds each time a signal corresponding to the pulse signal makes a circuit of the loop within said first delay circuit bank; a transmitter that parallel inputs output of said adder, synchronizes with said pulse signal, and parallel outputs each output; and a subtracter that parallel inputs output of said transmitter and subtracts each time the signal corresponding to said pulse signal makes a circuit of the loop within said second delay circuit bank.

Claim 8

A multiplex synchronous delay circuit according to claim 1 wherein each of said synchronous delay circuits comprises: an input delay adjustment circuit that inputs a signal corresponding to said pulse signal and equally adjusts each of said delay time differentials; a first delay circuit bank made up of a plurality of gate sections in cascade connection that inputs and sequentially delays output of said input delay adjustment circuit and parallel outputs output of each of said gate sections in the order of the gate sections from the input side; a latch circuit that parallel inputs output of each gate section of said first delay circuit bank, synchronizes with said pulse signal, and latches and parallel outputs each result; a second delay circuit bank made up of a plurality of gate sections in cascade connection arranged in the same direction as the signal transmission patch of said first delay circuit bank that inputs and sequentially delays said pulse signal and parallel outputs output of each of said gate sections in the order of the gate sections from the input side; a control circuit that parallel inputs output of each gate section of said second delay circuit bank, controls each input in accordance with each parallel output of said latch circuit, and, wired OR outputs the results; and an output delay adjustment circuit that inputs output of said control circuit, equally adjusts each of said delay time differentials, and outputs the result as one of said delay signals.

Claim 9

A multiplex synchronous delay circuit comprising: a plurality of synchronous delay circuits, wherein input pulse signals are input into a plurality of gate sections in cascade connection within each of said synchronous delay circuits, and said input pulse signals are transmitted through said gate sections in sequential delays, and said gate sections output in parallel and are synchronized with said input pulse signals, and wherein, based on each output in parallel, delay signals output from said plurality of synchronous delay circuits have a fixed delay time corresponding to said input pulse signals, and delay time differentials between said plurality of synchronous delay circuit means are maintained in sequential order; and a multiplex circuit that inputs each of said delay signals, multiplexes said delay signals, and outputs the result as multiplex delay signals.

Claim 10

A multiplex synchronous delay circuit comprising: a plurality of synchronous delay circuits, wherein input pulse signals are input into a plurality of gate sections in cascade connection within each of said synchronous delay circuits, and said input pulse signals are transmitted through said gate sections in sequential delays, and said gate sections output in parallel and are synchronized with said input pulse signals, and wherein, based on each output in parallel, delay signals output from said plurality of synchronous delay circuits have a fixed delay time corresponding to said input pulse signals, and delay time differentials between said plurality of synchronous delay circuit means are maintained in sequential order; and a multiplex circuit that inputs each of said delay signals, multiplexes said delay signals, and outputs the result as multiplex delay signals.

Claim 11

A multiplex synchronous delay circuit according to claim 8 wherein each of said synchronous delay circuit comprises: an input delay adjustment circuit that inputs a signal corresponding to said pulse signal and equally adjusts each of said delay time differentials; a first delay circuit bank made up of a plurality of gate sections in cascade connection that inputs and sequentially delays output of said input delay adjustment circuit and parallel outputs output of each of said gate sections in the order of the gate sections starting from the input side; a control circuit that parallel inputs output of each gate section of said first delay circuit bank, synchronizes with said pulse signal, and parallel outputs each result; a second delay circuit bank made up of a plurality of gate sections in cascade connection arranged in the reverse direction of the signal transmission path of said first delay circuit bank that parallel inputs to each gate section each output of said control circuit in the order of said gate sections from the output side, sequentially delays these inputs, and outputs the result; and an output delay adjustment circuit that inputs output of said second delay circuit bank, equally adjusts each of said delay time differentials, and outputs the result as one of said delay signals.

Claim 12

A multiplex synchronous delay circuit according to claim 9 wherein said second delay circuit bank comprises m rows of delay circuit sub-banks each made up of a plurality of gate sections in cascade connection arranged in the reverse direction of the signal transmission path of said first delay circuit bank, and the (d)th delay circuit sub-bank of said m rows of delay circuit sub-banks includes a circuit for parallel inputting to every (n)th gate section from the output side the output of every (m)th gate section from the (d)th gate section of said control circuit, sequentially delays these inputs, and outputs the result; a circuit for maintaining equal delay time differentials with respect to output of each of these m rows of delay circuit sub-banks and sequentially outputting the result; and a circuit for multiplexing these outputs and outputting the result to said output delay adjustment circuit.

Claim 13

A multiplex synchronous delay circuit according to claim 10 wherein said second delay circuit bank comprises: m sub-output delay adjustment circuits that input output of each of said m rows of delay circuit sub-banks, equally adjust each of said sub-delay time differentials, and output the result; and a sub-multiplex circuit that inputs outputs of said m sub-output delay adjustment circuits, multiplexes said output, and outputs the result.

Claim 14

A multiplex synchronous delay circuit according to claim 8 wherein each of said synchronous delay circuits comprises: an input delay adjustment circuit that inputs a signal corresponding to said pulse signal and equally adjusts each of said delay time differentials; a first delay circuit bank made up of a plurality of gate sections in cascade connection and loop connection that inputs and sequentially delays output of said input delay adjustment circuit and parallel outputs output of each of said gate sections in the order of the gate sections from the input side; a control circuit that parallel inputs output of each gate section of said first delay circuit bank, synchronizes with said pulse signal, and parallel outputs each result; a second delay circuit bank made up of a plurality of gate sections in cascade connection and loop connection arranged in the reverse direction of the signal transmission path of said first delay circuit bank that parallel inputs to each gate section each output of said control circuit in the order of the gate sections from the output side, sequentially delays these inputs, and outputs the result; counting circuit that adds each time a signal corresponding to said pulse signal makes a circuit of the loop within said first delay circuit bank, subtracts each time a signal corresponding to said pulse signal makes a circuit of the loop in said second delay circuit bank, and outputs a signal indicating that the number of circuits completed in said first and second delay circuit banks are equal; a selector circuit that, in accordance with output of said counting circuit, extracts from output a signal corresponding to said pulse signal circulating within said second delay circuit bank; and an output delay adjustment circuit that inputs output of said selector circuit, equally adjusts each of said delay time differentials, and outputs the result as one of said delay signals.

Claim 15

A multiplex synchronous delay circuit according to claim 12 wherein said counting circuit comprises: an adder that adds each time a signal corresponding to the pulse signal makes a circuit of the loop within said first delay circuit bank; a transmitter that parallel inputs output of said adder, synchronizes with said pulse signal, and parallel outputs each output; and a subtracter that parallel inputs output of said transmitter and subtracts each time the signal corresponding to said pulse signal makes a circuit of the loop within said second delay circuit bank.

Claim 16

A multiplex synchronous delay circuit according to claim 8 wherein each of said synchronous delay circuits comprises: an input delay adjustment circuit that inputs a signal corresponding to said pulse signal and equally adjust each of said delay time differentials; a first delay circuit bank made up of a plurality of gate sections in cascade connection that inputs and sequentially delays output of said input delay adjustment circuit and parallel outputs output of each of said gate sections in the order of the gate sections from the input side; a latch circuit that parallel inputs output of each gate section of said first delay circuit bank, synchronizes with said pulse signal, and latches and parallel outputs each result; a second delay circuit bank made up of a plurality of gate sections in cascade connection arranged in the same direction as the signal transmission patch of said first delay circuit bank that inputs and sequentially delays said pulse signal and parallel outputs output of each of said gate sections in the order of the gate sections from the input side; a control circuit that parallel inputs output of each gate section of said second delay circuit bank, controls each input in accordance with each parallel output of said latch circuit, and wired OR outputs the results; and an output delay adjustment circuit that inputs output of said control circuit, equally adjusts each of said delay time differentials, and outputs the result as one of said delay signals.