US7015739B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit devices having duty cycle correction circuits that receive control signals over first and second separate paths and methods of operating the same
Assignee: Samsung Electronics Co Ltd
•
Filing: 2004-03-04
•
Granted: 2006-03-21
•
Expires: 2024-03-04
Abstract
Abstract Digital duty cycle correction circuits are provided including a duty cycle detector circuit configured to generate first and second control values associated with a first internal clock signal and a second internal clock signal, respectively. A comparator circuit is also provided and is configured to compare the first control value to the second control value and provide a comparison result. A counter circuit is configured to perform an addition and/or a subtraction operation responsive to the comparison result to provide a digital code. A digital to analog converter is configured to generate third and fourth control values responsive to the digital code. Finally, a duty cycle corrector circuit is configured to receive first and second external clock signals and the first through fourth control values and generate the first and second internal clock signals having a corrected duty cycle. The first and second control values are received over a first path and the third and fourth control values are received over a second path, different from the first path. Related methods of operating duty cycle correction circuits are also provided.
Inventors
- 👤 Woo-Jin Lee
- 👤 Kyu-hyoun Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:36
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/156; H03K5/1565; G; G11; G11C; G11C8/00
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
165 words
A digital duty cycle correction circuit, comprising: a duty cycle detector circuit configured to generate first and second control values associated with a first internal clock signal and a second internal clock signal, respectively; a comparator circuit configured to compare the first control value to the second control value and provide a comparison result; a counter circuit configured to perform an addition or a subtraction operation responsive to the comparison result to provide a digital code; a digital to analog converter configured to generate third and fourth control values responsive to the digital code; and a duty cycle corrector circuit configured to receive the first through fourth control values and generate the first and second internal clock signals having a corrected duty cycle, the first and second control values being received at the duty cycle corrector circuit over a first path and the third and fourth control values being received at the duty cycle corrector circuit over a second path, separate from the first path.
Claim 2
Dependent Claim
165 words
A digital duty cycle correction circuit, comprising: a duty cycle detector circuit configured to generate first and second control values associated with a first internal clock signal and a second internal clock signal, respectively; a comparator circuit configured to compare the first control value to the second control value and provide a comparison result; a counter circuit configured to perform an addition or a subtraction operation responsive to the comparison result to provide a digital code; a digital to analog converter configured to generate third and fourth control values responsive to the digital code; and a duty cycle corrector circuit configured to receive the first through fourth control values and generate the first and second internal clock signals having a corrected duty cycle, the first and second control values being received at the duty cycle corrector circuit over a first path and the third and fourth control values being received at the duty cycle corrector circuit over a second path, separate from the first path.
Claim 3
Dependent Claim
47 words
The duty cycle correction circuit of claim 1 , wherein the first and second control values are directly provided to the duty corrector circuit over the first path and the third and fourth control values are directly provided to the duty corrector circuit over the second path.
Claim 4
Dependent Claim
39 words
The duty cycle correction circuit of claim 1 , wherein the duty cycle detector circuit comprises a first charge pump configured to generate the first control value and a second charge pump configured to generate the second control value.
Claim 5
Dependent Claim
48 words
The duty cycle correction circuit of claim 3 , wherein the first and second charge pumps comprise first and second capacitors, respectively, wherein the first control value comprises an average charge of the first capacitor and the second control value comprises an average charge of the second capacitor.
Claim 6
Dependent Claim
77 words
The duty cycle correction circuit of claim 1 , wherein the comparison result comprises a logic high signal or a logic low signal, wherein the comparator circuit is further configured to compare the first control value and the second control value and generate the logic high signal if the first control value is greater than the second control value and generate the logic low signal if the second control value is greater than the first control value.
Claim 7
Dependent Claim
48 words
The duty cycle correction circuit of claim 5 , wherein the counter circuit is further configured to receive the logic high signal or the logic low signal and perform the addition operation responsive to the logic high signal and the subtraction operation responsive to the logic low signal.
Claim 8
Dependent Claim
28 words
The duty cycle correction circuit if claim 1 , wherein the duty cycle correction circuit comprises a differential amplifier and wherein the corrected duty cycle is about 50%.
Claim 9
Dependent Claim
174 words
A digital duty cycle correction circuit, comprising: a duty cycle corrector circuit configured to receive first and second external clock signals and first through fourth control values and generate first and second internal clock signals having a corrected duty cycle, the first and second control values being received at the duty cycle corrector circuit over a first path and the third and fourth control values being received at the duty cycle corrector circuit over a second path, separate from the first path; a duty cycle detector circuit configured to generate the first and the second control values associated with the first internal clock signal and the second internal clock signal, respectively; a comparator circuit configured to compare the first control value to the second control value and provide a comparison result; a counter circuit configured to perform an addition and/or a subtraction operation responsive to the comparison result to provide a digital code; and a digital to analog converter configured to generate the third and the fourth control values responsive to the digital code.
Claim 10
Dependent Claim
174 words
A digital duty cycle correction circuit, comprising: a duty cycle corrector circuit configured to receive first and second external clock signals and first through fourth control values and generate first and second internal clock signals having a corrected duty cycle, the first and second control values being received at the duty cycle corrector circuit over a first path and the third and fourth control values being received at the duty cycle corrector circuit over a second path, separate from the first path; a duty cycle detector circuit configured to generate the first and the second control values associated with the first internal clock signal and the second internal clock signal, respectively; a comparator circuit configured to compare the first control value to the second control value and provide a comparison result; a counter circuit configured to perform an addition and/or a subtraction operation responsive to the comparison result to provide a digital code; and a digital to analog converter configured to generate the third and the fourth control values responsive to the digital code.
Claim 11
Dependent Claim
47 words
The duty cycle correction circuit of claim 8 , wherein the first and second control values are directly provided to the duty corrector circuit over the first path and the third and fourth control values are directly provided to the duty corrector circuit over the second path.
Claim 12
Dependent Claim
27 words
The duty cycle correction circuit if claim 9 , wherein the duty cycle correction circuit comprises a differential amplifier and wherein the duty cycle is about 50%.
Claim 13
Dependent Claim
39 words
The duty cycle correction circuit of claim 8 , wherein the duty cycle detector circuit comprises a first charge pump configured to generate the first control value and a second charge pump configured to generate the second control value.
Claim 14
Dependent Claim
48 words
The duty cycle correction circuit of claim 11 , wherein the first and second charge pumps comprise first and second capacitors, respectively, wherein the first control value comprises an average charge of the first capacitor and the second control value comprises an average charge of the second capacitor.
Claim 15
Dependent Claim
77 words
The duty cycle correction circuit of claim 8 , wherein the comparison result comprises a logic high signal or a logic low signal, wherein the comparator circuit is further configured to compare the first control value and the second control value and generate the logic high signal if the first control value is greater than the second control value and generate the logic low signal if the second control value is greater than the first control value.
Claim 16
Dependent Claim
48 words
The duty cycle correction circuit of claim 13 , wherein the counter circuit is further configured to receive the logic high signal and/or the logic low signal and perform the addition operation responsive to the logic high signal and the subtraction operation responsive to the logic low signal.
Claim 17
Independent Claim
168 words
A method of operating a duty cycle correction circuit, comprising: generating first and the second control values associated with a first internal clock signal and a second internal clock signal, respectively; comparing the first control value to the second control value to provide a comparison result; performing an addition or a subtraction operation responsive to the comparison result to provide a digital code; generating third and the fourth control values responsive to the digital code; receiving the first and second external clock signals and the first through fourth control values at a duty cycle corrector circuit, the first and second control values being received at the duty cycle corrector circuit over a first path and the third and fourth control values being received at the duty cycle corrector circuit over a second path, separate from the first path; and generating the first and second internal clock signals having a corrected duty cycle responsive to the first and second external clock signals and the first through fourth control values.
Claim 18
Independent Claim
168 words
A method of operating a duty cycle correction circuit, comprising: generating first and the second control values associated with a first internal clock signal and a second internal clock signal, respectively; comparing the first control value to the second control value to provide a comparison result; performing an addition or a subtraction operation responsive to the comparison result to provide a digital code; generating third and the fourth control values responsive to the digital code; receiving the first and second external clock signals and the first through fourth control values at a duty cycle corrector circuit, the first and second control values being received at the duty cycle corrector circuit over a first path and the third and fourth control values being received at the duty cycle corrector circuit over a second path, separate from the first path; and generating the first and second internal clock signals having a corrected duty cycle responsive to the first and second external clock signals and the first through fourth control values.
Claim 19
Dependent Claim
46 words
The method of claim 15 , wherein comparing is followed by: generating a logic high signal if the first control value is greater than the second control value; and generating a logic low signal if the second control value is greater than the first control value.
Claim 20
Dependent Claim
56 words
The method of claim 16 , wherein generating the logic high signal or the logic low signal is followed by: receiving the logic high signal or the logic low signal and wherein performing further comprises performing the addition operation responsive to the logic high signal and performing the subtraction operation responsive to the logic low signal.
References Cited (Backward Citations)
US5155397A
Cited
US5572158A
Cited
US6566925B2
Cited
US6373309B1
Cited
KR20020044191A
Cited
US6525581B1
Cited
US6583657B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-03-20 | 2009-09-19 | 2010-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-03-20 | 2013-09-19 | 2014-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-03-20 | 2017-09-19 | 2018-03-21 | $7700.00 | Window Closed / Lapsed |