Duty correction circuit and a method of correcting a duty

Claim 2

A duty correction circuit comprising: a duty check block connected to a clock signal and a clock bar signal for determining a duty of the clock signal or the clock bar signal, and generating a control signal indicating a determination result; and a duty correction block for receiving the clock signal and the clock bar signal, having a phase difference of 180° from the clock signal, correcting the duty of one of the clock signal or clock bar signal according to the control signal from the duty check block, and outputting the duty-corrected signal.

Claim 3

The circuit according to claim 1 , wherein the duty check block determines whether the duty of the clock signal is 50%, below 50% or over 50%.

Claim 4

The circuit according to claim 2 , wherein the duty correction unit corrects the duty of the clock signal when the duty of the clock signal is below 50%, corrects the duty of the clock bar signal when the duty of the clock signal is over 50%, and outputs the clock signal or clock bar signal without duty correction when the duty of the clock signal is 50%.

Claim 5

The circuit according to claim 1 , wherein the duty check block comprises: a first switch controlled according to the clock signal; a second switch controlled according to the clock bar signal; a first capacitor charged or discharged by an on or off state of the first switch; and a second capacitor charged or discharged by an on or off state of the second switch.

Claim 6

The circuit according to claim 4 , wherein the duty check block further comprises a comparator for comparing the voltage applied to the first capacitor with the voltage applied to the second capacitor, and for generating the control signal.

Claim 7

The circuit according to claim 1 , wherein the duty correction unit comprises: a clock signal correction unit enabled according to the control signal for correcting the duty of the clock signal when the duty of the clock signal is below 50%; and a clock bar signal correction unit enabled according to the control signal for correcting the duty of the clock bar signal when the duty of the clock signal is over 50%.

Claim 8

The circuit according to claim 6 , wherein the clock signal correction unit comprises: a first phase blending circuit for enabling the clock signal to have a predetermined slope; a first delay circuit for delaying the clock signal for a predetermined time; and a second phase blending circuit for enabling the output signal from the first delay circuit to have a predetermined slope, the first phase blending circuit and the second phase blending circuit having their output terminals electrically connected.

Claim 9

The circuit according to claim 6 , wherein the clock bar signal correction unit comprises: a third phase blending circuit for enabling the clock bar signal to have a predetermined slope; a second delay circuit for delaying the clock bar signal for a predetermined time; and a fourth phase blending circuit for enabling the output signal from the second delay circuit to have a predetermined slope, the third phase blending circuit and the fourth phase blending circuit having their output terminals electrically connected.

Claim 10

The circuit according to claim 1 , further comprising a clock buffer block for receiving the output signal from the duty correction unit, and generating a new clock signal and a new clock bar signal which have a phase difference of 180° with respect to each other.

Claim 11

The circuit according to claim 9 , wherein the clock buffer unit comprises two inverter chains for receiving the output signal from the duty correction unit, one inverter chain comprising an even number of inverters, and the other inverter chain comprising an odd number of inverters.

Claim 12

A duty correction circuit comprising: a duty check block connected to a clock signal and a clock bar signal for determining whether a duty of the clock signal is 50%, below 50% or over 50%, and generating a control signal indicating a determination result; and a duty correction block for receiving the clock signal and the clock bar signal having a phase difference of 180° with respect to the clock signal, correcting the duty of the clock signal when the duty of the clock signal is below 50%, correcting the duty of the clock bar signal when the duty of the clock signal is over 50%, and outputting the clock signal or clock bar signal without duty correction when the duty of the clock signal is 50%.

Claim 13

A duty correction circuit comprising: a duty check block connected to a clock signal and a clock bar signal for determining whether a duty of the clock signal is 50%, below 50% or over 50%, and generating a control signal indicating a determination result; and a duty correction block for receiving the clock signal and the clock bar signal having a phase difference of 180° with respect to the clock signal, correcting the duty of the clock signal when the duty of the clock signal is below 50%, correcting the duty of the clock bar signal when the duty of the clock signal is over 50%, and outputting the clock signal or clock bar signal without duty correction when the duty of the clock signal is 50%.

Claim 14

The circuit according to claim 11 , wherein the duty check block comprises: a first switch controlled according to the clock signal; a second switch controlled according to the clock bar signal; a first capacitor charged or discharged by an on or off state of the first switch; a second capacitor charged or discharged by an on or off state of the second switch; and a comparator for comparing the voltage applied to the first capacitor with the voltage applied to the second capacitor, and for generating the control signal.

Claim 15

The circuit according to claim 11 , wherein the duty correction unit comprises: a clock signal correction unit enabled according to the control signal for correcting the duty of the clock signal when the duty of the clock signal is below 50%; and a clock bar signal correction unit enabled according to the control signal for correcting the duty of the clock bar signal when the duty of the clock signal is over 50%, wherein the clock signal correction unit further comprises: a first phase blending circuit for enabling the clock signal to have a predetermined slope; a first delay circuit for delaying the clock signal for a predetermined time; and a second phase blending circuit for enabling the output signal from the first delay circuit to have a predetermined slope, the first and second phase blending circuits having their output terminals electrically connected, and wherein the clock bar signal correction unit further comprises: a third phase blending circuit for enabling the clock bar signal to have a predetermined slope; a second delay circuit for delaying the clock bar signal for a predetermined time; and a fourth phase blending circuit for enabling the output signal from the second delay circuit to have a predetermined slope, the third and fourth phase blending circuits having their output terminals electrically connected.

Claim 16

The circuit according to claim 11 , further comprising a clock buffer block for receiving the output signal from the duty correction unit, and generating a new clock signal and a new clock bar signal which have a phase difference of 180° with respect to each other.

Claim 17

The circuit according to claim 14 , wherein the clock buffer unit comprises two inverter chains for receiving the output signal from the duty correction unit, one inverter chain comprising an even number of inverters, and the other inverter chain comprising an odd number of inverters.

Claim 20

The method according to claim 16 , wherein the correction of the clock signal in the duty check step comprises: a first step for enabling the clock signal to have a predetermined slope; a second step for delaying the clock signal, and enabling the delayed clock signal to have a predetermined slope; and a third step for blending the resulting signals of the first and second steps.

Claim 21

The method according to claim 17 , wherein the correction of the clock bar signal in the duty check step further comprises: a fourth step for enabling the clock bar signal to have a predetermined slope; a fifth step for delaying the clock bar signal, and enabling the delayed clock bar signal to have a predetermined slope; and a sixth step for blending the resulting signals of the fourth and fifth steps.

Claim 22

The circuit according to claim 16 , further comprising a clock buffering step that comprises receiving the output signal of the duty correction step, and generating a new clock signal and a new clock bar signal which have a phase difference of 180° with respect to each other.

Claim 23

The circuit according to claim 19 , wherein the clock buffering step further comprises: a step for enabling the output signal of the duty correction step to pass through an inverter chain having an even number of inverters; and a step for enabling the output signal of the duty correction step to pass through an inverter chain having an odd number of inverters.