US6169434B1
Expired / Lapsed
US
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Conversion circuit with duty cycle correction for small swing signals, and associated method
Assignee: Rambus Inc
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Filing: 1998-09-03
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Granted: 2001-01-02
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Expires: 2018-09-03
Abstract
Abstract A duty cycle correcting amplifier includes a first differential transistor pair with a pair of input nodes for receiving a differential input signal to be amplified. The first differential transistor pair has a first common node and a first pair of output nodes carrying differential output signals. A first current source is connected between the first common node and a first supply voltage. A second differential transistor pair has a pair of input nodes for receiving differential error input signals. The second differential transistor pair has a second common node and a second pair of output nodes coupled to the first pair of output nodes. The second differential transistor pair alters the common mode levels of each of the first pair of output nodes based on the differential error input signals to affect the duty cycle of the differential output signals. A second current source is connected between the second common node and the first supply voltage. A load circuit is connected between the first pair of output nodes and a second supply voltage. The load circuit provides a high impedance load between each node of the first pair of output nodes and a low impedance between each node of the first pair of output nodes and the second supply voltage. Capacitive circuitry is connected to each node of the first pair of output nodes. A converting amplifier has a pair of inputs for receiving the differential output signals. The converting amplifier amplifies and converts the differential output signals to a single ended signal constituting the output of the duty cycle correcting amplifier.
Inventors
- 👤 Clemenz L. Portmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:37
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/156; H03K5/1565
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
260 words
A duty cycle correcting amplifier, comprising: a first differential transistor pair with a pair of input nodes for receiving a differential input signal to be amplified, said first differential transistor pair having a first common node and a first pair of output nodes carrying differential output signals; a first current source connected between said first common node and a first supply voltage; a second differential transistor pair having a pair of input nodes for receiving differential error input signals, said second differential transistor pair having a second common node and a second pair of output nodes coupled to said first pair of output nodes, said second differential transistor pair altering the common mode levels of each of said first pair of output nodes based on said differential error input signals to affect the duty cycle of said differential output signals; a second current source connected between said second common node and said first supply voltage; a load circuit connected between said first pair of output nodes and a second supply voltage, said load circuit providing a high impedance load between each node of said first pair of output nodes and a low impedance between each node of said first pair of output nodes and said second supply voltage; capacitive circuitry connected to each node of said first pair of output nodes; and a converting amplifier having a pair of inputs for receiving said differential output signals, said converting amplifier amplifying and converting said differential output signals to a single ended signal constituting the output of said duty cycle correcting amplifier.
Claim 2
Dependent Claim
260 words
A duty cycle correcting amplifier, comprising: a first differential transistor pair with a pair of input nodes for receiving a differential input signal to be amplified, said first differential transistor pair having a first common node and a first pair of output nodes carrying differential output signals; a first current source connected between said first common node and a first supply voltage; a second differential transistor pair having a pair of input nodes for receiving differential error input signals, said second differential transistor pair having a second common node and a second pair of output nodes coupled to said first pair of output nodes, said second differential transistor pair altering the common mode levels of each of said first pair of output nodes based on said differential error input signals to affect the duty cycle of said differential output signals; a second current source connected between said second common node and said first supply voltage; a load circuit connected between said first pair of output nodes and a second supply voltage, said load circuit providing a high impedance load between each node of said first pair of output nodes and a low impedance between each node of said first pair of output nodes and said second supply voltage; capacitive circuitry connected to each node of said first pair of output nodes; and a converting amplifier having a pair of inputs for receiving said differential output signals, said converting amplifier amplifying and converting said differential output signals to a single ended signal constituting the output of said duty cycle correcting amplifier.
Claim 3
Dependent Claim
31 words
The duty cycle correcting amplifier of claim 1 wherein said load circuit includes a set of PMOS transistors connected between said first pair of output nodes and said second supply voltage.
Claim 4
Dependent Claim
14 words
The duty cycle correcting amplifier of claim 1 in combination with a dynamic memory.
Claim 5
Dependent Claim
204 words
An amplifier, comprising: a first transistor coupled between a first internal node and a first supply voltage, said first transistor being controlled by a signal received at a first amplifier input node; a second transistor coupled between a second internal node and said first supply voltage, said second transistor being controlled by a signal received at a second amplifier input node; a third transistor coupled between a second supply voltage and said first internal node, said third transistor being controlled by a signal received at said first internal node; a fourth transistor coupled between said second supply voltage and said second internal node, said fourth transistor being controlled by a signal received at said second internal node; a fifth transistor coupled between said second supply voltage and said first internal node, said fifth transistor being controlled by a signal received at said second internal node; a sixth transistor coupled between said second supply voltage and said second internal node, said sixth transistor being controlled by a signal received at said first internal node; and a converting amplifier connected to said third, fourth, fifth, and sixth transistors to convert differential signals from said third, fourth, fifth, and sixth transistors to a single ended output signal.
Claim 6
Dependent Claim
204 words
An amplifier, comprising: a first transistor coupled between a first internal node and a first supply voltage, said first transistor being controlled by a signal received at a first amplifier input node; a second transistor coupled between a second internal node and said first supply voltage, said second transistor being controlled by a signal received at a second amplifier input node; a third transistor coupled between a second supply voltage and said first internal node, said third transistor being controlled by a signal received at said first internal node; a fourth transistor coupled between said second supply voltage and said second internal node, said fourth transistor being controlled by a signal received at said second internal node; a fifth transistor coupled between said second supply voltage and said first internal node, said fifth transistor being controlled by a signal received at said second internal node; a sixth transistor coupled between said second supply voltage and said second internal node, said sixth transistor being controlled by a signal received at said first internal node; and a converting amplifier connected to said third, fourth, fifth, and sixth transistors to convert differential signals from said third, fourth, fifth, and sixth transistors to a single ended output signal.
Claim 7
Dependent Claim
78 words
The amplifier of claim 4 further comprising: a seventh transistor coupled between said first internal node and said first supply voltage, said seventh transistor being controlled by a first error signal received at a first error signal input node of said amplifier; and an eighth transistor coupled between said second internal node and said first supply voltage, said eighth transistor being controlled by a second error signal received at a second error signal input node of said amplifier.
Claim 8
Dependent Claim
16 words
The amplifier of claim 4 wherein said third, fourth, fifth, and sixth transistors are PMOS transistors.
Claim 9
Dependent Claim
22 words
The amplifier of claim 4 wherein a current source is coupled between said first and second transistors and said first supply voltage.
Claim 10
Dependent Claim
22 words
The amplifier of claim 5 wherein a current source is coupled between said seventh and eighth transistors and said first supply voltage.
Claim 11
Dependent Claim
11 words
The amplifier of claim 4 in combination with a dynamic memory.
References Cited (Backward Citations)
US5696724A
Cited
US5696726A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2004-01-02 | 2004-07-03 | 2005-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-02 | 2008-07-03 | 2009-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-02 | 2012-07-03 | 2013-01-02 | $7700.00 | Window Closed / Lapsed |