US5696724A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sense amplifier
Assignee: SK Hynix Inc
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Filing: 1996-12-16
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Granted: 1997-12-09
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Expires: 2016-12-16
Abstract
Abstract A sense amplifier comprising a data refresh amplifier for supplying voltages to true and complementary bit lines in response to a first control signal to amplify true and complementary data on the true and complementary bit lines, respectively, a first transistor for amplifying current of the true data on the true bit line in response to a second control signal and transferring the amplified true data to a true input/output line, a second transistor for amplifying current of the complementary data on the complementary bit line in response to the second control signal and transferring the amplified complementary data to a complementary input/output line, a first switch for selectively forming a current path between the true input/output line and the true bit line, and a second switch for selectively forming a current path between the complementary input/output line and the complementary bit line.
Inventors
- 👤 Yo Hwan Koh
- 👤 Chan Kwang Park
- 👤 Jeung Won Suh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:15
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C11/4094; G11C11/4096; G11C7/00; G11C7/06; G11C7/062
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
218 words
A bit line sense amplifier comprising: a) data refresh amplification means for supplying voltages to true and complementary bit lines in response to a first control signal to amplify true and complementary data on the true and complementary bit lines, respectively; b) first current amplification means for amplifying current of the true data on the true bit line in response to a second control signal and for transferring the amplified true data to a complementary node; c) second current amplification means for amplifying current of the complementary data on the complementary bit line in response to the second control signal and for transferring the amplified complementary data to a true node; d) first feedback means for controllably forming a path between: d1) the true node; and d2) the true bit line at a point on the true bit line adjacent the first current amplification means; e) second feedback means for controllably forming a path between: e1) the complementary node; and e2) the complementary bit line at a point on the complementary bit line adjacent the second current amplification means; f) first switching means for selectively forming a current path between the true node and a true input/output line; and g) second switching means for selectively forming a current path between the complementary node and a complementary input/output line.
Claim 2
Dependent Claim
218 words
A bit line sense amplifier comprising: a) data refresh amplification means for supplying voltages to true and complementary bit lines in response to a first control signal to amplify true and complementary data on the true and complementary bit lines, respectively; b) first current amplification means for amplifying current of the true data on the true bit line in response to a second control signal and for transferring the amplified true data to a complementary node; c) second current amplification means for amplifying current of the complementary data on the complementary bit line in response to the second control signal and for transferring the amplified complementary data to a true node; d) first feedback means for controllably forming a path between: d1) the true node; and d2) the true bit line at a point on the true bit line adjacent the first current amplification means; e) second feedback means for controllably forming a path between: e1) the complementary node; and e2) the complementary bit line at a point on the complementary bit line adjacent the second current amplification means; f) first switching means for selectively forming a current path between the true node and a true input/output line; and g) second switching means for selectively forming a current path between the complementary node and a complementary input/output line.
Claim 3
Dependent Claim
78 words
The bit line sense amplifier of claim 1, wherein the data refresh amplification means includes: a1) a first PMOS transistor that is selectively driven in response to the complementary data from the complementary bit line to transfer the first control signal to the true bit line; and a2) a second PMOS transistor that is selectively driven in response to the true data from the true bit line to transfer the first control signal to the complementary bit line.
References Cited (Backward Citations)
US4644196A
Cited
US4831287A
Cited
US4973864A
Cited
US4871933A
Cited
US5016224A
Cited
US5241503A
Cited
US5457657A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-08 | 2001-06-09 | 2001-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-08 | 2005-06-09 | 2005-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-08 | 2009-06-09 | 2009-12-09 | $7700.00 | Window Closed / Lapsed |