US5457657A
Expired / Lapsed
US
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High-speed sense amplifier having feedback loop
Assignee: SK Hynix Inc
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Filing: 1994-09-21
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Granted: 1995-10-10
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Expires: 2014-09-21
Abstract
Abstract A high-speed sense amplifier for a memory device with at least one memory cell, comprising true and complementary bit lines connected to the memory cell, a differential amplification circuit for inputting true and complementary bit data through the true and complementary bit lines, amplifying the inputted true and complementary bit data and transferring the amplified true and complementary bit data to true and complementary data bus lines, respectively, a first feedback loop for feeding the amplified true bit data on the true data bus line back to the memory cell through the true bit line, and a second feedback loop for feeding the amplified complementary bit data on the complementary data bus line back to the memory cell through the complementary bit line. According to the invention, the high-speed sense amplifier can sense and amplify the data on the true and complementary bit lines at a high speed. Therefore, an access speed of the memory device can be enhanced.
Inventors
- 👤 Jeung W. Suh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:13
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/06; G11C7/065; G11C7/062
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
122 words
A high-speed sense amplifier for a memory device with at least one memory cell, comprising: true and complementary bit lines connected to said memory cell; differential amplification means for inputting true and complementary bit data through said true and complementary bit lines, amplifying the inputted true and complementary bit data and transferring the amplified true and complementary bit data to true and complementary data bus lines, respectively; a first feedback loop for feeding the amplified true bit data on said true data bus line back to said memory cell through said complementary bit line; and a second feedback loop for feeding the amplified complementary bit data on said complementary data bus line back to said memory cell through said true bit line.
Claim 2
Dependent Claim
122 words
A high-speed sense amplifier for a memory device with at least one memory cell, comprising: true and complementary bit lines connected to said memory cell; differential amplification means for inputting true and complementary bit data through said true and complementary bit lines, amplifying the inputted true and complementary bit data and transferring the amplified true and complementary bit data to true and complementary data bus lines, respectively; a first feedback loop for feeding the amplified true bit data on said true data bus line back to said memory cell through said complementary bit line; and a second feedback loop for feeding the amplified complementary bit data on said complementary data bus line back to said memory cell through said true bit line.
Claim 3
Dependent Claim
38 words
A high-speed sense amplifier as set forth in claim 1, wherein said first and second feedback loops are driven after a lapse of a predetermined time period from an operation start time point of said differential amplification means.
Claim 4
Dependent Claim
161 words
A high-speed sense amplifier as set forth in claim 2, wherein said differential amplification means includes: first switching means for switching a first control signal of high logic from a first control signal input line to said true data bus line in response to the true bit data from said true bit line; second switching means for switching the first control signal from said first control signal input line to said complementary data bus line in response to the complementary bit data from said complementary bit line; third switching means for switching a second control signal of low logic from a second control signal input line to said true data bus line in response to the complementary bit data from said complementary data bus line; and fourth switching means for switching the second control signal from said second control signal input line to said complementary data bus line in response to the true bit data from said true data bus line.
Claim 5
Dependent Claim
23 words
A high-speed sense amplifier as set forth in claim 3, wherein each of said first to fourth switching means includes an MOS transistor.
Claim 6
Dependent Claim
122 words
A high-speed sense amplifier for a memory device with at least one memory cell, comprising: true and complementary bit lines connected to said memory cell; differential amplification means for inputting true and complementary bit data through said true and complementary bit lines, inverse-amplifying the inputted true and complementary bit data and transferring the inverse-amplified true and complementary bit data to true and complementary data bus lines, respectively; a first feedback loop for feeding the inverse-amplified true bit data on said true data bus line back to said memory cell through said complementary bit line; and a second feedback loop for feeding the inverse-amplified complementary bit data on said complementary data bus line back to said memory cell through said true bit line.
Claim 7
Dependent Claim
122 words
A high-speed sense amplifier for a memory device with at least one memory cell, comprising: true and complementary bit lines connected to said memory cell; differential amplification means for inputting true and complementary bit data through said true and complementary bit lines, inverse-amplifying the inputted true and complementary bit data and transferring the inverse-amplified true and complementary bit data to true and complementary data bus lines, respectively; a first feedback loop for feeding the inverse-amplified true bit data on said true data bus line back to said memory cell through said complementary bit line; and a second feedback loop for feeding the inverse-amplified complementary bit data on said complementary data bus line back to said memory cell through said true bit line.
Claim 8
Dependent Claim
161 words
A high-speed sense amplifier as set forth in claim 5, wherein said differential amplification means includes: first switching means for switching a first control signal of high logic from a first control signal input line to said true data bus line in response to the true bit data from said true bit line; second switching means for switching the first control signal from said first control signal input line to said complementary data bus line in response to the complementary bit data from said complementary bit line; third switching means for switching a second control signal of low logic from a second control signal input line to said true data bus line in response to the complementary bit data from said complementary data bus line; and fourth switching means for switching the second control signal from said second control signal input line to said complementary data bus line in response to the true bit data from said true data bus line.
Claim 9
Dependent Claim
36 words
A high-speed sense amplifier as set forth in claim 6, wherein each of said first and second switching means includes a PMOS transistor and each of said third and fourth switching means includes an NMOS transistor.
Claim 10
Dependent Claim
38 words
A high-speed sense amplifier as set forth in claim 5, wherein said first and second feedback loops are driven after a lapse of a predetermined time period from an operation start time point of said differential amplification means.
Claim 11
Dependent Claim
50 words
A high-speed sense amplifier as set forth in claim 5, further comprising: equalization means being driven in complementary cooperation with said differential amplification means for electrically connecting said true and complementary data bus lines to each other to enhance a precharge speed of said true and complementary data bus lines.
References Cited (Backward Citations)
US4027176A
Cited
JPS5457921A
Cited
US4247791A
Cited
US4697112A
Cited
US5126974A
Cited
US5155397A
Cited
US5189322A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-09 | 1999-04-10 | 1999-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-09 | 2003-04-10 | 2003-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-09 | 2007-04-10 | 2007-10-10 | $7700.00 | Window Closed / Lapsed |