High-speed static differential sense amplifier

Claim 2

A high-speed static differential sense amplifier, including: a noninverting input node, an inverting input node, an inverting output, a non-inverting output, a first source follower connected to said noninverting input node, a second source follower connected to said inverting input node, a first pull-up current mirror having a current reference portion connected to said first source follower and an output driver portion connected to said noninverting output, a second pull-up current mirror having a current reference portion connected to said second source follower and an output driver poriton connected to said inverting output, a first pull-down current mirror having a current reference portion connected to said second source follower and an output driver portion connected to said noninverting output, a second pull-down current mirror having a current reference portion connected between said first source follower and an output driver portion connected to said noninverting output.

Claim 3

A high-speed static differential sense amplifier, including: a noninverting input node, an inverting input node, a first N-channel input transistor having its gate connected to said noninverting input node, a second N-channel input transistor having its gate connected to said inverting input node, a third N-channel input transistor having its source connected to a source of negative voltage and its drain connected to the source of said first N-channel input transistor, a fourth N-channel input transistor having its source connected to a source of negative voltage, its gate connected to the drain of said third N-channel input transistor and its drain connected to the source of said second N-channel input transistor and to the gate of said third N-channel input transistor, a first P-channel input transistor having its source connected to a source of positive voltage, its drain and gate connected to the drain of said first N-channel input transistor, a second P-channel input transistor having its source connected to a source of positive voltage and its drain and gate connected to the drain of said second N-channel input transistor, a first N-channel output transistor having its source connected to a source of negative voltage, its gate connected to the source of said first N-channel input transistor and its drain connected to a noninverting output node, a first P-channel output transistor having its source connected to a source of positive voltage, its gate connected to the drain of said first N-channel input transistor and its drain connected to said noninverting output node, a second N-channel output transistor having its source connected to a source of negative voltage, its gate connected to the source of said second N-channel input transistor and its drain connected to an inverting output node, a second P-channel output transistor having its source connected to a source of positive voltage, its gate connected to the drain of said second N-channel input transistor and its drain connected to said inverting output node.

Claim 4

A high-speed static differential sense amplifier, including: a noninverting input node, an inverting input node, a first N-channel input transistor having its gate connected to said noninverting input node, a second N-channel input transistor having its gate connected to said inverting input node, a third N-channel input transistor having its source connected to a source of negative voltage and its drain connected to the source of said first N-channel input transistor, a fourth N-channel input transistor having its source connected to a source of negative voltage, its gate connected to the drain of said third N-channel input transistor and its drain connected to the source of said second N-channel input transistor and to the gate of said third N-channel input transistor, a first P-channel input transistor having its source connected to a source of positive voltage, its drain and gate connected to the drain of said first N-channel input transistor, a second P-channel input transistor having its source connected to a source of positive voltage and its drain and gate connected to the drain of said second N-channel input transistor, a first N-channel output transistor having its source connected to a source of negative voltage, its gate connected to the source of said first N-channel input transistor and its drain connected to a noninverting output node, a first P-channel output transistor having its source connected to a source of positive voltage, its gate connected to the drain of said first N-channel input transistor and its drain connected to said noninverting output node, a second N-channel output transistor having its source connected to a source of negative voltage, its gate connected to the source of said second N-channel input transistor and its drain connected to an inverting output node, a second P-channel output transistor having its source connected to a source of positive voltage, its gate connected to the drain of said second N-channel input transistor and its drain connected to said inverting output node.