Complementary differential amplifier in which direct current amplification gain can be set arbitrarily and semiconductor memory divice using the same

Claim 2

A complementary differential amplifier for amplifying difference in potential level between complementary inputs to generate complementary outputs, comprising: cascade-connected internal differential amplifying means of a plurality of stages for receiving said complementary inputs as complementary inputs to a first stage to sequentially amplifying said received complementary inputs, wherein each of said internal differential amplifying means includes a pair of first and second internal output nodes where complementary internal outputs are produced, respectively, a pair of first and second MOS transistors of a first conductivity type having their sources coupled to a first power supply potential, their gates cross-connected to their drains, and their drains respectively connected to said pair of internal output nodes, third and fourth diode-connected MOS transistors of the first conductivity type respectively connected in parallel to said pair of MOS transistors of the first conductivity type and between said first power supply and said pair of internal output nodes, and driving means connected between said pair of internal output nodes and a second power supply for driving said first to fourth MOS transistors in response to said complementary inputs in the case of the first stage and to said complementary internal outputs of the preceding stage in the case of subsequent stages, wherein both said first and second MOS transistors have a first size, and both said third and fourth MOS transistors have a second size, said second size being larger than said first size, where MOS transistor size is defined by (gate width)/(gate length).

Claim 3

The complementary differential amplifier according to claim 1, wherein said driving means includes a current source connected to said second power supply, and a pair of fifth and sixth MOS transistors of a second conductivity type having their sources connected to said current source, their gates respectively receiving said complementary inputs in the case of the first stage and receiving said complementary internal outputs of the preceding stage in the case of subsequent stages, and their drains respectively connected to said internal output nodes.

Claim 4

The complementary differential amplifier according to claim 2, wherein said complementary differential amplifier is a two-stage amplifier including first and second internal differential amplifying means, and said internal output nodes of said first internal differential amplifying means are directly connected to the gates of said fifth and said sixth MOS transistors in said driving means of said second internal differential amplifying means, respectively.

Claim 5

The complementary differential amplifier according to claim 2, wherein said internal differential amplifying means of said first stage of said complementary differential amplifier further includes a seventh MOS transistor of the first conductivity type and an eighth MOS transistor of the second conductivity type connected in series between said first power supply and said current source with a third internal output node interposed therebetween, a ninth MOS transistor of the first conductivity type and a tenth MOS transistor of the second conductivity type connected in series between said first power supply and said current source With a fourth internal output node interposed therebetween, wherein a gate of said eighth MOS transistor receives one of said complementary inputs, in common with the gate of said fifth MOS transistor, a gate of said seventh MOS transistor is connected to said second internal output node, a gate of said tenth MOS transistor receives another input of said complementary inputs, in common with a gate of said sixth MOS transistor, a gate of said ninth MOS transistor is connected to said first internal output node, and said third and fourth internal output nodes are connected to inputs of the subsequent stage, respectively.

Claim 6

The complementary differential amplifier according to claim 4, wherein said complementary differential amplifier is a two-stage amplifier including first and second internal differential amplifying means, said third and fourth internal output nodes of said first internal differential amplifying means are connected to the gates of said fifth and sixth MOS transistors in said driving means of said second internal differential amplifying means, respectively, and potentials at said first and second internal output nodes of said second internal differential amplifying means are output as said complementary outputs.

Claim 7

The complementary differential amplifier according to claim 3, wherein a current source of said first internal differential amplifying means is an MOS transistor of the second conductivity type for receiving a differential amplifier activation signal at its gate.

Claim 8

The complementary differential amplifier according to claim 5, wherein a current source of said first internal differential amplifying means is an MOS transistor of the second conductivity type for receiving a differential amplifier activation signal at its gate.

Claim 9

The complementary differential amplifier according to claim 3, wherein a current source of said second internal differential amplifying means is an MOS transistor of the second conductivity type for receiving a differential amplifier activation signal at its gate.

Claim 10

The complementary differential amplifier according to claim 5, wherein a current source of said second internal differential amplifying means is an MOS transistor of the second conductivity type for receiving a differential amplifier activation signal at its gate.

Claim 11

A semiconductor memory device, comprising: a memory cell array including a plurality of word lines, a plurality of bit line pairs located across said plurality of word lines, and a plurality of memory cells connected to said word lines and said bit line pairs; a plurality of I/O line pairs each connected to said bit line pairs through switching means; and a plurality of complementary differential amplifiers provided corresponding to said plurality of I/O line pairs to operate selectively for receiving as complementary inputs and amplifying potential difference between a corresponding I/O line pair, wherein each of said complementary differential amplifiers includes cascade-connected internal differential amplifying means of a plurality of stages for receiving said complementary inputs as complementary inputs of a first stage to sequentially amplify said received complementary inputs, and each of said internal differential amplifying means includes a pair of first and second internal output nodes where complementary internal outputs are produced, a pair of first and second MOS transistors of a first conductivity type having their sources coupled to a first power supply potential, their gates cross-connected to their drains, and their drains respectively connected to said pair of internal output nodes, and diode-connected third and fourth MOS transistors of a first conductivity type respectively connected in parallel to said pair of MOS transistors of a first conductivity type and between said first power supply and said pair of internal output nodes, wherein both said first and second MOS transistors have a first size, and both said third and fourth MOS transistors have a second size, said second size being larger than said first size, and each of said internal differential amplifying means further includes driving means connected between said pair of internal output nodes and a second power supply for driving said first to fourth MOS transistors in response to said complementary inputs in the case of a first stage and to said complementary internal outputs of the preceding stage in the case of subsequent stages, where MOS transistor size is defined by (gate width)/(gate length).

Claim 12

A semiconductor memory device, comprising: a memory cell array including a plurality of word lines, a plurality of bit line pairs located across said plurality of word lines, and a plurality of memory cells connected to said word lines and said bit line pairs; a plurality of I/O line pairs each connected to said bit line pairs through switching means; and a plurality of complementary differential amplifiers provided corresponding to said plurality of I/O line pairs to operate selectively for receiving as complementary inputs and amplifying potential difference between a corresponding I/O line pair, wherein each of said complementary differential amplifiers includes cascade-connected internal differential amplifying means of a plurality of stages for receiving said complementary inputs as complementary inputs of a first stage to sequentially amplify said received complementary inputs, and each of said internal differential amplifying means includes a pair of first and second internal output nodes where complementary internal outputs are produced, a pair of first and second MOS transistors of a first conductivity type having their sources coupled to a first power supply potential, their gates cross-connected to their drains, and their drains respectively connected to said pair of internal output nodes, and diode-connected third and fourth MOS transistors of a first conductivity type respectively connected in parallel to said pair of MOS transistors of a first conductivity type and between said first power supply and said pair of internal output nodes, wherein both said first and second MOS transistors have a first size, and both said third and fourth MOS transistors have a second size, said second size being larger than said first size, and each of said internal differential amplifying means further includes driving means connected between said pair of internal output nodes and a second power supply for driving said first to fourth MOS transistors in response to said complementary inputs in the case of a first stage and to said complementary internal outputs of the preceding stage in the case of subsequent stages, where MOS transistor size is defined by (gate width)/(gate length).

Claim 13

The semiconductor memory device according to claim 10, further comprising a first data line for transmitting a first output signal out of complementary outputs of said complementary differential amplifier; a second data line for transmitting a second output signal out of said complementary outputs of said complementary differential amplifier; driving means for transmitting said first and second output signals to said first and second data lines, respectively; and output buffer means for receiving signals from said first and second data lines to be rendered in a high impedance state or in a signal output state in response to potentials of the signals, wherein said output buffer means transitions from being in said high impedance state to being in said signal output state according to difference in potential level between signals from said first and second data lines.

Claim 14

A complementary differential amplifier for amplifying difference in potential level between complementary inputs to generate complementary outputs, comprising: a pair of first and second MOS transistors of a first conductivity type having their sources coupled to a first power supply, their gates cross-connected to their drains, and their drains respectively connected to first and second internal output nodes; third diode-connected MOS transistors of the first conductivity type connected in parallel to said first MOS transistors of the first conductivity type and between said first power supply and said first internal output nodes; fourth diode-connected MOS transistors of the first conductivity type connected in parallel to said second MOS transistors of the first conductivity type and between said first power supply and said second internal output nodes; a current source connected between a second power supply and an internal power supply node; fifth and sixth MOS transistors of a second conductivity type having their sources connected to said internal power supply node, their gates respectively receiving said complementary inputs, and their drains respectively connected to said first and second internal output nodes; a seventh MOS transistor of the first conductivity type and an eight MOS transistor of the second conductivity type connected in series between said first power supply and said internal power supply node with a third internal output node interposed therebetween; and a ninth MOS transistor of the first conductivity type and a tenth MOS transistor of the second conductivity type connected in series between said first power supply and said internal power supply node with a fourth internal output node interposed therebetween, wherein a gate of said eighth MOS transistor receives one of said complementary inputs, in common with the gate of said fifth MOS transistor, a gate of said seventh MOS transistor is connected to said second internal output node, a gate of said tenth MOS transistor receives the other of said complementary inputs, in common with a gate of said sixth MOS transistor, a gate of said ninth MOS transistor is connected to said first internal output node, a potential level of said third internal output node is driven to the level corresponding to one of said complementary outputs, and a potential level of said fourth internal output node is driven to the level corresponding to the other of said complementary outputs.

Claim 15

A complementary differential amplifier for amplifying difference in potential level between complementary inputs to generate complementary outputs, comprising: a pair of first and second MOS transistors of a first conductivity type having their sources coupled to a first power supply, their gates cross-connected to their drains, and their drains respectively connected to first and second internal output nodes; third diode-connected MOS transistors of the first conductivity type connected in parallel to said first MOS transistors of the first conductivity type and between said first power supply and said first internal output nodes; fourth diode-connected MOS transistors of the first conductivity type connected in parallel to said second MOS transistors of the first conductivity type and between said first power supply and said second internal output nodes; a current source connected between a second power supply and an internal power supply node; fifth and sixth MOS transistors of a second conductivity type having their sources connected to said internal power supply node, their gates respectively receiving said complementary inputs, and their drains respectively connected to said first and second internal output nodes; a seventh MOS transistor of the first conductivity type and an eight MOS transistor of the second conductivity type connected in series between said first power supply and said internal power supply node with a third internal output node interposed therebetween; and a ninth MOS transistor of the first conductivity type and a tenth MOS transistor of the second conductivity type connected in series between said first power supply and said internal power supply node with a fourth internal output node interposed therebetween, wherein a gate of said eighth MOS transistor receives one of said complementary inputs, in common with the gate of said fifth MOS transistor, a gate of said seventh MOS transistor is connected to said second internal output node, a gate of said tenth MOS transistor receives the other of said complementary inputs, in common with a gate of said sixth MOS transistor, a gate of said ninth MOS transistor is connected to said first internal output node, a potential level of said third internal output node is driven to the level corresponding to one of said complementary outputs, and a potential level of said fourth internal output node is driven to the level corresponding to the other of said complementary outputs.