US6952333B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
ESD protection circuit for high-voltage, high DV/DT pads
Assignee: National Semiconductor Corp
•
Filing: 2003-09-15
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Granted: 2005-10-04
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Expires: 2023-09-15
Abstract
Abstract A pad that experiences a high-voltage, high dV/dT signal during normal operation is prevented from falsely triggering by utilizing a bipolar transistor connected to the pad to provide ESD protection, and a MOS transistor connected to the bipolar transistor to turn off the bipolar transistor during normal circuit operation.
Inventors
- 👤 Douglas Robert Farrenkopf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:02
CPC Classifications
H; H02; H02H; H02H9/00; H02H9/04; H02H9/045; H02H9/046
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
61 words
An ESD protection circuit comprising: a pad; a to-be-protected circuit connected to the pad; a MOS transistor having a drain, a source, and a gate; and an npn bipolar junction transistor having a collector connected to the pad, an emitter connected to a ground line, and a base connected to the drain, only a single drain being connected to the base.
Claim 2
Dependent Claim
61 words
An ESD protection circuit comprising: a pad; a to-be-protected circuit connected to the pad; a MOS transistor having a drain, a source, and a gate; and an npn bipolar junction transistor having a collector connected to the pad, an emitter connected to a ground line, and a base connected to the drain, only a single drain being connected to the base.
Claim 3
Dependent Claim
27 words
The ESD protection circuit of claim 1 and further comprising a delay line having an input, and an output connected to the gate of the MOS transistor.
Claim 4
Dependent Claim
21 words
The ESD protection circuit of claim 2 and further comprising a resistive device connected to the base and the ground line.
Claim 5
Dependent Claim
35 words
The ESD protection circuit of claim 2 and further comprising: a first resistive device connected to the base and the ground line; and a second resistive device connected to the gate and the ground line.
Claim 6
Dependent Claim
21 words
The ESD protection circuit of claim 2 wherein the input of the delay line is connected to a power supply pad.
Claim 7
Dependent Claim
37 words
The ESD protection circuit of claim 2 wherein the delay line has a delay period required for a signal to pass through the delay line, the delay period being greater than a period of an ESD event.
Claim 8
Dependent Claim
60 words
An ESD protection circuit comprising: a pad; a to-be-protected circuit connected to the pad; an NMOS transistor having a drain, a source, and a gate; and an npn bipolar junction transistor having a collector connected to the pad, an emitter connected to a ground line, and a base connected to the drain, no PMOS transistor being connected to the base.
Claim 9
Dependent Claim
60 words
An ESD protection circuit comprising: a pad; a to-be-protected circuit connected to the pad; an NMOS transistor having a drain, a source, and a gate; and an npn bipolar junction transistor having a collector connected to the pad, an emitter connected to a ground line, and a base connected to the drain, no PMOS transistor being connected to the base.
Claim 10
Dependent Claim
27 words
The ESD protection circuit of claim 7 and further comprising a delay line having an input, and an output connected to the gate of the NMOS transistor.
Claim 11
Dependent Claim
21 words
The ESD protection circuit of claim 8 and further comprising a resistive device connected to the base and the ground line.
Claim 12
Dependent Claim
35 words
The ESD protection circuit of claim 8 and further comprising: a first resistive device connected to the base and the ground line; and a second resistive device connected to the gate and the ground line.
Claim 13
Dependent Claim
21 words
The ESD protection circuit of claim 8 wherein the input of the delay line is connected to a power supply pad.
Claim 14
Dependent Claim
37 words
The ESD protection circuit of claim 8 wherein the delay line has a delay period required for a signal to pass through the delay line, the delay period being greater than a period of an ESD event.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-10-03 | 2009-04-04 | 2009-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-10-03 | 2013-04-04 | 2013-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-10-03 | 2017-04-04 | 2017-10-04 | $7700.00 | Window Closed / Lapsed |