Active Vcc-to-Vss ESD clamp with hystersis for low supply chips

Claim 2

A protection circuit comprising: a clamping transistor, coupled to shunt current from an electro-static-discharge (ESD) pulse, having a control gate; a voltage divider, coupled to the ESD pulse, for generating a divided voltage being a predetermined fraction of a voltage of the ESD pulse; a chain of inverters, receiving the divided voltage, for driving the control gate of the clamping transistor; and an extending transistor, for driving an extended internal node in the chain of inverters, having a gate receiving a feedback voltage from another internal node in the chain of inverters after the extended internal node; whereby the extending transistor extends a discharge time that the clamping transistor is shunting current during the ESD pulse.

Claim 3

The protection circuit of claim 1 further comprising: a hysteresis transistor, coupled to drive an output of an inverter in the chain of inverters, for increasing a divided voltage required to turn on the control gate of the clamping transistor, whereby a higher turn-on voltage is required.

Claim 4

The protection circuit of claim 2 wherein the hysteresis transistor is a transistor that couples a first internal node in the chain of inverters to a power supply, the hysteresis transistor having a gate coupled to a second internal node after the first internal node, the second internal node being driven by an inverter that has the first internal node as an input, whereby hysteresis is provided by coupling to the power supply.

Claim 5

The protection circuit of claim 3 wherein the hysteresis transistor is a p-channel transistor.

Claim 6

The protection circuit of claim 4 wherein the clamping transistor is an n-channel transistor.

Claim 7

The protection circuit of claim 5 wherein the clamping transistor has a drain coupled to a power supply, and a source coupled to a ground, whereby the clamping transistor shunts current from power to ground when the ESD pulse is applied from a power pin to a ground pin.

Claim 8

The protection circuit of claim 6 wherein the extending transistor is an n-channel transistor coupled between the extended internal node and the ground.

Claim 9

The protection circuit of claim 7 wherein the extending transistor has a gate coupled to the control gate of the clamping transistor, whereby the extending transistor and the clamping transistor share a common gate node.

Claim 10

The protection circuit of claim 8 wherein the chain of inverters includes a first inverter that receives the divided voltage from the voltage divider to output the first internal node, a second inverter that receives the first internal node and outputs the second internal node, a third inverter that receives the second internal node and outputs the extended internal node, and a fourth inverter that receives the extended internal node and drives the control gate of the clamping transistor, whereby four inverters are in the chain of inverters.

Claim 11

The protection circuit of claim 8 further comprising: filter capacitors, coupled to the voltage divider, for capacitivly coupling the divided voltage to the ground and to the power supply, whereby the divided voltage is capacitivly coupled to the power supply and to the ground.

Claim 12

The protection circuit of claim 10 wherein the voltage divider comprises two resistors in series.

Claim 13

A Vcc-to-Vss electro-static-discharge (ESD) protection circuit comprising: a Vcc power supply; a Vss ground supply; a voltage divider coupled between the Vcc power supply and the Vss ground supply, for generating a divided voltage on a sense node; a chain of inverters, receiving the divided voltage, for generating a control node, the chain of inverters having an extended node; a clamping transistor, having a channel for conducting current from the Vcc power supply to the Vss ground supply in response to the control node; and an extending transistor, having a channel for conducting current from the extended node to the Vss ground supply in response to a feedback voltage, the feedback voltage having an opposite logic state as the extended node, whereby the extending transistor uses the feedback voltage to extend discharge through the clamping transistor.

Claim 14

A Vcc-to-Vss electro-static-discharge (ESD) protection circuit comprising: a Vcc power supply; a Vss ground supply; a voltage divider coupled between the Vcc power supply and the Vss ground supply, for generating a divided voltage on a sense node; a chain of inverters, receiving the divided voltage, for generating a control node, the chain of inverters having an extended node; a clamping transistor, having a channel for conducting current from the Vcc power supply to the Vss ground supply in response to the control node; and an extending transistor, having a channel for conducting current from the extended node to the Vss ground supply in response to a feedback voltage, the feedback voltage having an opposite logic state as the extended node, whereby the extending transistor uses the feedback voltage to extend discharge through the clamping transistor.

Claim 15

The Vcc-to-Vss ESD protection circuit of claim 12 wherein the chain of inverters comprises an even number of inverting stages.

Claim 16

The Vcc-to-Vss ESD protection circuit of claim 13 wherein the clamping transistor and the extending transistor are n-channel metal-oxide-semiconductor (MOS) transistors.

Claim 17

The Vcc-to-Vss ESD protection circuit of claim 12 wherein the feedback voltage is a voltage of the control node, whereby the control node is fed back to the extending transistor.

Claim 18

Vcc-to-Vss ESD protection circuit of claim 12 wherein the chain of inverters comprises: a first inverter, receiving the divided voltage, for outputting a second node; a second inverter, receiving the second node, for driving a third node; a third inverter, receiving the third node, for driving the extended node; a fourth inverter, receiving the extended node, for driving the control node.

Claim 19

Vcc-to-Vss ESD protection circuit of claim 16 further comprising: a hysteresis transistor, having a gate coupled to the third node, for conducting current from the Vcc power supply to the second node; wherein a switching threshold of the first inverter is increased by the hysteresis transistor, whereby noise immunity is increased by the hysteresis transistor.

Claim 20

A core protection device for protecting core transistors from electro-static-discharge (ESD) pulses comprising: a clamping n-channel transistor, having a drain coupled to a power supply bus, a source coupled to a ground bus, and a gate coupled to a control node, for shunting current during ESD pulses; a final inverter receiving an extended node, for outputting the control node; an extending n-channel transistor, having a drain coupled to the extended node, a source coupled to the ground bus, and a gate coupled to the control node, for extending discharge time when the clamping n-channel transistor is turned on during the ESD pulses; at least one inverter, receiving a third node, for outputting to the extended node; a second inverter, receiving a second node, for outputting the third node; a first inverter, receiving a first node, for outputting the second node; a first resistor, coupled between the power supply bus and the first node; and a second resistor, coupled between the first node and the ground bus; the first and second resistors for generating a sense voltage on the first node, the sense voltage being proportional to a voltage between the power supply bus and the ground bus; wherein a switching threshold of the first inverter is lower than the sense voltage when the voltage between the power supply bus and the ground bus is within a normal operating range, the clamping n-channel transistor being turned off; wherein when the voltage between the power supply bus and the ground bus is above the normal operating range during an ESD pulse, the sense voltage exceeds the switching threshold, and the clamping n-channel transistor is turned on, whereby discharge time is extended by the extending n-channel transistor.

Claim 21

A core protection device for protecting core transistors from electro-static-discharge (ESD) pulses comprising: a clamping n-channel transistor, having a drain coupled to a power supply bus, a source coupled to a ground bus, and a gate coupled to a control node, for shunting current during ESD pulses; a final inverter receiving an extended node, for outputting the control node; an extending n-channel transistor, having a drain coupled to the extended node, a source coupled to the ground bus, and a gate coupled to the control node, for extending discharge time when the clamping n-channel transistor is turned on during the ESD pulses; at least one inverter, receiving a third node, for outputting to the extended node; a second inverter, receiving a second node, for outputting the third node; a first inverter, receiving a first node, for outputting the second node; a first resistor, coupled between the power supply bus and the first node; and a second resistor, coupled between the first node and the ground bus; the first and second resistors for generating a sense voltage on the first node, the sense voltage being proportional to a voltage between the power supply bus and the ground bus; wherein a switching threshold of the first inverter is lower than the sense voltage when the voltage between the power supply bus and the ground bus is within a normal operating range, the clamping n-channel transistor being turned off; wherein when the voltage between the power supply bus and the ground bus is above the normal operating range during an ESD pulse, the sense voltage exceeds the switching threshold, and the clamping n-channel transistor is turned on, whereby discharge time is extended by the extending n-channel transistor.

Claim 22

The core protection device of claim 18 further comprising: a hysteresis p-channel transistor, having a drain coupled to the second node, a source coupled to the power supply bus, and a gate coupled to the third node, for raising the switching threshold of the first inverter when the sense voltage is rising, whereby the switching threshold is raised for rising sense voltages to provide noise suppression.

Claim 23

The core protection device of claim 19 further comprising: a first filter capacitor, coupled between the power supply bus and the first node; a second filter capacitor, coupled between the first node and the ground bus, whereby the sense voltage is filtered.