US6908227B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for thermal management of multiple core microprocessors
Assignee: Sony Corp of America
•
Filing: 2002-08-23
•
Granted: 2005-06-21
•
Expires: 2022-08-23
Abstract
Abstract An apparatus for managing the temperature of an integrated circuit having a multiple core microprocessor is described. Specifically, thermal sensors are placed at potential hot spots throughout each microprocessor core. A thermal management unit monitors the thermal sensors. If a thermal sensor identifies a hot spot, the thermal management unit adjusts the operating frequency and voltage of that microprocessor core accordingly.
Inventors
- 👤 Stefan Rusu
- 👤 Simon M. Tam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:32
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/16; G06F1/20; G06F1/206; G01; G01K; G01K1/00; G01K1/02; G01K1/026; G01K7/00; G01K7/42; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/324; G06F1/3296; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
179 words
A system comprising: a first thermal sensor sensing a first temperature of the system and generating a first digital signal having a frequency representing the first temperature; a second thermal sensor sensing a second temperature of the system and generating a second digital signal having a frequency representing the second temperature, wherein the second temperature is a reference temperature; a first counter coupled to the first thermal sensor and enabled by the first digital signal, the first counter counts in a first direction in response to a transition of the first digital signal; a second counter coupled to the second thermal sensor and enabled by the second digital signal, the second counter counts in a second direction in response to a transition of the second digital signal; and a digital controller coupled to the first counter and the second counter, wherein the digital controller compares the count values of the first counter and the second counter, wherein if the second counter reaches a target value before the first counter, the digital controller decreases an operating voltage of the system.
Claim 2
Independent Claim
179 words
A system comprising: a first thermal sensor sensing a first temperature of the system and generating a first digital signal having a frequency representing the first temperature; a second thermal sensor sensing a second temperature of the system and generating a second digital signal having a frequency representing the second temperature, wherein the second temperature is a reference temperature; a first counter coupled to the first thermal sensor and enabled by the first digital signal, the first counter counts in a first direction in response to a transition of the first digital signal; a second counter coupled to the second thermal sensor and enabled by the second digital signal, the second counter counts in a second direction in response to a transition of the second digital signal; and a digital controller coupled to the first counter and the second counter, wherein the digital controller compares the count values of the first counter and the second counter, wherein if the second counter reaches a target value before the first counter, the digital controller decreases an operating voltage of the system.
Claim 3
Dependent Claim
16 words
The system of claim 1 , wherein the operating voltage decrease is at a step value.
Claim 4
Dependent Claim
17 words
The system of claim 1 , wherein the digital controller adjusts an operating frequency of the system.
Claim 5
Independent Claim
66 words
A method comprising: monitoring a reference thermal sensor; monitoring a plurality of thermal sensors placed in a processor having a first and a second processor core; and increasing an operating frequency of the first processor core to improve throughput of the first processor core if a temperature at the reference thermal sensor is greater than a temperature at a thermal sensor in the first processor core.
Claim 6
Independent Claim
66 words
A method comprising: monitoring a reference thermal sensor; monitoring a plurality of thermal sensors placed in a processor having a first and a second processor core; and increasing an operating frequency of the first processor core to improve throughput of the first processor core if a temperature at the reference thermal sensor is greater than a temperature at a thermal sensor in the first processor core.
Claim 7
Dependent Claim
32 words
The method of claim 4 , further comprising: decreasing an operating voltage of the first processor core if the temperature at the thermal sensor exceeds the temperature at the reference thermal sensor.
Claim 8
Dependent Claim
37 words
The method of claim 5 , wherein the operating voltage adjustment is made according to a look-up table, wherein the greater the temperature at the reference thermal sensor is exceeded, the greater the operating voltage is adjusted.
Claim 9
Dependent Claim
25 words
The method of claim 4 , wherein the plurality of thermal sensors sense the temperature of a floating point unit of the first processor core.
Claim 10
Dependent Claim
25 words
The method of claim 4 , wherein the plurality of thermal sensors sense the temperature of an integer execution unit of the first processor core.
References Cited (Backward Citations)
US4300048A
Cited
US4551031A
Cited
US5495617A
Cited
US5046858A
Cited
US5307003A
Cited
US5153535A
Cited
US5021679A
Cited
US20020007463A1
Cited
EP0549165A2
Cited
US5373254A
Cited
US6078356A
Cited
US5287292A
Cited
EP0592783A2
Cited
US5392437A
Cited
US5838578A
Cited
US5557551A
Cited
US5422806A
Cited
US6487668B2
Cited
US5752011A
Cited
US6216235B1
Cited
US5974557A
Cited
US5723998A
Cited
US5822369A
Cited
US5627412A
Cited
US6192479B1
Cited
WO1999017186A1
Cited
US5719800A
Cited
US5745375A
Cited
US5825674A
Cited
US5766228A
Cited
US5815724A
Cited
US5940785A
Cited
US6047248A
Cited
US5781783A
Cited
US6029006A
Cited
US5832284A
Cited
US5829879A
Cited
US6105142A
Cited
US5835885A
Cited
US5902044A
Cited
US5964881A
Cited
US6219796B1
Cited
US6559631B1
Cited
US6091255A
Cited
US6172611B1
Cited
US20010021217A1
Cited
US6393374B1
Cited
US6789037B2
Cited
US6470289B1
Cited
US6211740B1
Cited
US6407595B1
Cited
US6460005B1
Cited
US6718474B1
Cited
US20020084905A1
Cited
US20020143488A1
Cited
US20030110012A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-06-20 | 2008-12-20 | 2009-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-06-20 | 2012-12-20 | 2013-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-06-20 | 2016-12-20 | 2017-06-21 | $7700.00 | Window Closed / Lapsed |