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US5835885A Expired / Lapsed US ⏱️ 0.0 years remaining

Over temperature protection method and device for a central processing unit

Assignee: Giga Byte Technology Co Ltd
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Filing: 1997-06-05
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Granted: 1998-11-10
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Expires: 2017-06-05
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Abstract

Abstract An over temperature protection method and its circuital device for a central processing unit includes a read and write memory unit having pre-stored therein; an instruction for identifying a type of CPU and automatically predetermining the maximum allowable over temperature for the CPU. An over temperature is detected by a heat sensitive resistance installed at the space immediately under the CPU to cause an audio frequency alarm circuit to output a sound alarm and also cause the CPU to slow down its operation speed to an appropriate reduced rate to prevent CPU from being damaged by over heat or other loss caused by interrupting CPU operation. After recovery of temperature to a normal value, the CPU can be instructed to operate with its normal speed.

Inventors

  • 👤 Huo-Yuan Lin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 14:21
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/16; G06F1/20; G06F1/206

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 370 words
An over temperature protection method for a central processing unit (CPU), comprising the steps of: first, pre-storing an on/off instruction and an instruction for identifying a type of CPU in a read and write memory unit of a basic input/output system (BIOS) circuit when the CPU is initialized, and causing the CPU to directly read the instruction from said BIOS memory unit and instruct a chip circuit to operate, and at the same time energizing a main switch of an on/off function circuit, second, selecting a mode for a temperature detecting mode select circuit based on identification by said CPU of its own type, and matching the selected mode with a temperature sensing heat sensitive resistance installed adjacently under said CPU so that as a working temperature of the CPU rises, the value of temperature heat sensitive resistance linearly varies, and the potential of a resistor connected to one terminal of the temperature heat sensitive resistance also varies inverse proportionally to a starting value, until the working temperature of the CPU has reached a predetermined value, third, actuating an over temperature circuit to output a signal to an over temperature alarm circuit for energizing the over temperature alarm circuit, at which time, since both the on/off circuit and the over temperature alarm circuit are mutually cascadely grounded, an audio frequency alarm circuit controlled by the functional on/off circuit is energized, fourth, outputting an audible alarm from said audio frequency alarm circuit and sending said signal to the chip circuit via another circuit, fifth, outputting a signal from said chip circuit to a frequency eliminating circuit to initiate the frequency eliminating circuit, sixth, inputting the output from said frequency eliminator circuit to a frequency eliminating control circuit to split a system clock signal output by said chip circuit to slow down an operation speed of the CPU, and, finally, after the heat generation by the CPU is reduced due to said slow down to a value which is able to ensure that the CPU will work continuously without interrupting flow of information being processed, and an over temperature hazard is released, returning the over temperature circuit to a de-energized state and restoring other circuits to their normal state without any output.
Claim 2
Dependent Claim 370 words
An over temperature protection method for a central processing unit (CPU), comprising the steps of: first, pre-storing an on/off instruction and an instruction for identifying a type of CPU in a read and write memory unit of a basic input/output system (BIOS) circuit when the CPU is initialized, and causing the CPU to directly read the instruction from said BIOS memory unit and instruct a chip circuit to operate, and at the same time energizing a main switch of an on/off function circuit, second, selecting a mode for a temperature detecting mode select circuit based on identification by said CPU of its own type, and matching the selected mode with a temperature sensing heat sensitive resistance installed adjacently under said CPU so that as a working temperature of the CPU rises, the value of temperature heat sensitive resistance linearly varies, and the potential of a resistor connected to one terminal of the temperature heat sensitive resistance also varies inverse proportionally to a starting value, until the working temperature of the CPU has reached a predetermined value, third, actuating an over temperature circuit to output a signal to an over temperature alarm circuit for energizing the over temperature alarm circuit, at which time, since both the on/off circuit and the over temperature alarm circuit are mutually cascadely grounded, an audio frequency alarm circuit controlled by the functional on/off circuit is energized, fourth, outputting an audible alarm from said audio frequency alarm circuit and sending said signal to the chip circuit via another circuit, fifth, outputting a signal from said chip circuit to a frequency eliminating circuit to initiate the frequency eliminating circuit, sixth, inputting the output from said frequency eliminator circuit to a frequency eliminating control circuit to split a system clock signal output by said chip circuit to slow down an operation speed of the CPU, and, finally, after the heat generation by the CPU is reduced due to said slow down to a value which is able to ensure that the CPU will work continuously without interrupting flow of information being processed, and an over temperature hazard is released, returning the over temperature circuit to a de-energized state and restoring other circuits to their normal state without any output.
Claim 3
Dependent Claim 24 words
The method as claimed in claim 1, wherein said temperature detecting heat sensitive resistance is installed in a space adjacently right under said CPU.
Claim 4
Dependent Claim 116 words
An over temperature protection circuit device for a central processing unit (CPU), comprising: a read and write memory unit of a basic input/output system (BIOS) circuit matched with the CPU of the computer; a chip circuit; a functional on/off circuit; a temperature detecting mode selection circuit principally formed of transistors Q 3 , Q 4 and at least one selection resistance connected in parallel; an over temperature actuating circuit; an over temperature alarm circuit: an audio frequency alarm circuit composed of oscillators, transistors and a speaker; a frequency eliminating circuit; and, a frequency eliminating control circuit, wherein said frequency eliminator circuit is enlarged and includes additional components to select other values of frequencies to be eliminated.
Claim 5
Dependent Claim 116 words
An over temperature protection circuit device for a central processing unit (CPU), comprising: a read and write memory unit of a basic input/output system (BIOS) circuit matched with the CPU of the computer; a chip circuit; a functional on/off circuit; a temperature detecting mode selection circuit principally formed of transistors Q 3 , Q 4 and at least one selection resistance connected in parallel; an over temperature actuating circuit; an over temperature alarm circuit: an audio frequency alarm circuit composed of oscillators, transistors and a speaker; a frequency eliminating circuit; and, a frequency eliminating control circuit, wherein said frequency eliminator circuit is enlarged and includes additional components to select other values of frequencies to be eliminated.
Claim 6
Dependent Claim 40 words
An over temperature protection circuit device as claimed in claim 3, wherein the resistance employed in said temperature detecting mode selection circuit is a resistance having a positive temperature coefficient of resistance for cooperatively operating with said heat sensitive resistance.

References Cited (Backward Citations)

US3876999A Cited
US5073861A Cited
US5025248A Cited
US5262758A Cited
US5398597A Cited
US5371665A Cited
US5566062A Cited
US5710911A Cited
US5619906A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-11-09 2002-05-11 2002-11-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-11-09 2006-05-11 2006-11-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-11-09 2010-05-11 2010-11-10 $7700.00 Window Closed / Lapsed

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