US6029006A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processor with circuit for regulating instruction throughput while powered and method of operation
Assignee: NXP USA Inc
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Filing: 1996-12-23
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Granted: 2000-02-22
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Expires: 2016-12-23
Abstract
Abstract A data processor (10) incorporates instruction regulating or "throttling" circuitry (31) for limiting consumed power. A user visible register maintains an INTERVAL field by which instruction fetch from an instruction cache (14) is periodically delayed. This INTERVAL field may be adjusted to suit the power budget of the data processor.
Inventors
- 👤 Michael Alexander
- 👤 Belliappa Kuttanna
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:50
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3867; G06F9/3869; G06F1/00; G06F1/26; G06F1/32; G06F9/3802; G06F9/3836; G06F9/3838; G06F9/384
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
181 words
A method of operating a data processor comprising the steps of: generating a first fetch address, the first fetch address indexing a first instruction; fetching the first instruction generating a second fetch address, the second fetch address indexing a second instruction; during a first time interval, executing the first instruction; and executing a loop comprising the steps of; comparing a first value to a predetermined number wherein the first value is user programmable; de-asserting an enable address signal responsive to being in a first power mode and to the first value not equaling the predetermined value, the data processor not fetching the second instruction while de-asserting the enable address signal; asserting the enable address signal responsive to being in a first power mode and to the first value equaling the predetermined value, the data processor fetching the second instruction while asserting the enable address signal; decrementing the first value during a second time interval, asserting the enable address signal responsive to being in a second power mode; and accessing a memory system responsive to the fetch address and enable address signal.
Claim 2
Independent Claim
181 words
A method of operating a data processor comprising the steps of: generating a first fetch address, the first fetch address indexing a first instruction; fetching the first instruction generating a second fetch address, the second fetch address indexing a second instruction; during a first time interval, executing the first instruction; and executing a loop comprising the steps of; comparing a first value to a predetermined number wherein the first value is user programmable; de-asserting an enable address signal responsive to being in a first power mode and to the first value not equaling the predetermined value, the data processor not fetching the second instruction while de-asserting the enable address signal; asserting the enable address signal responsive to being in a first power mode and to the first value equaling the predetermined value, the data processor fetching the second instruction while asserting the enable address signal; decrementing the first value during a second time interval, asserting the enable address signal responsive to being in a second power mode; and accessing a memory system responsive to the fetch address and enable address signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-21 | 2003-08-23 | 2004-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-21 | 2007-08-23 | 2008-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-21 | 2011-08-23 | 2012-02-22 | $7700.00 | Window Closed / Lapsed |