Clock distribution control circuit for conserving power in computer systems

Claim 2

A circuit for slowing or inhibiting the output of clock pulses to a microprocessor based system for a specific period of time, initiated by a specific trigger condition, comprising: a delay circuit for preventing the output of said system clock pulses for a variable length of time equal to a multiple of N clock pulses where N is a predetermined positive integer; means, coupled to said delay circuit, for inputting a first signal which begins a nap period during which said system clock pulses are prevented from being output from said delay circuit to said microprocessor based system; clock input means, coupled to said delay circuit, for providing a clock pulse signal as an input to said delay circuit which functions to control the operation of said microprocessor based system; and gate means, coupled to said delay circuit, for applying a second signal to said delay circuit in order to thereby terminate said nap period by permitting said clock pulse signal to be output from said delay circuit to said microprocessor based system.

Claim 3

The circuit according to Claim 2, wherein said clock input means comprises: means for selecting one of a plurality of different frequency clock pulse signals, each of which includes a plurality of synchronous clock pulses.

Claim 4

The circuit according to Claim 3, wherein said means for selecting one of said plurality of different frequency clock pulse signals comprises: a multiplexer.

Claim 5

The circuit according to Claim 4, wherein said multiplexer includes a plurality of first inputs for receiving said plurality of clock pulse signals and at least one second input for determining the frequency of the clock pulse signal which will be output to said delay circuit.

Claim 6

The circuit according to Claim 3, wherein said delay circuit comprises: a plurality of series-connected flip flop elements.

Claim 7

The circuit according to Claim 6, wherein said plurality of flip flop elements equals N in number.

Claim 8

The circuit according to Claim 7, wherein the output of the nth flip flop element is applied as an input to said delay circuit in order to control the input of said selected clock pulse signal to the first flip flop element of said N series-connected flip flop elements.

Claim 9

The circuit according to Claim 8, further comprising: a gate circuit which receives, as a first input, the selected clock pulse signal, and as a second input, the output of said nth flip flop element.

Claim 10

The circuit according to Claim 9, wherein said selected clock pulse signal is output from the delay circuit when the output of said nth flip flop element goes high.

Claim 12

The method according to Claim 11, wherein said step of providing said clock pulse signal of predetermined frequency as an input to said delay circuit comprises: selecting one of a plurality of different frequency clock pulse signals for input to said delay circuit.

Claim 13

The method according to Claim 12, wherein said step of providing said clock pulse signal of predetermined frequency as an input to said delay circuit further comprises: inputting a plurality of different frequency clock pulse signals to a multiplexer which receives at least one additional input signal for determining the clock pulse signal to be input to said delay circuit.

Claim 14

The method according to Claim 11, wherein said step of inhibiting said clock pulse signal from being output to said microprocessor based system comprises the step of: inputting a second external signal to a first circuit element of said delay circuit which prevents the clock pulse signal from being output to said microprocessor based system.

Claim 15

The method according to Claim 11, wherein said step of inhibiting said clock pulse signal from being output to said microprocessor based system further comprises the step of: maintaining an output signal of said delay circuit in a state which prevents the output of clock pulses to said microprocessor based system.

Claim 16

The method according to Claim 15, wherein said step of maintaining said output signal of said delay circuit in a state which prevents the output of clock pulses to said microprocessor based system comprises the steps of: maintaining the output of the nth flip flop element of N flip flop elements included in said delay circuit in a state which prevents said clock pulses from being output to said microprocessor based system.

Claim 17

The method according to Claim 16, further comprising the step of: applying a first high signal to the input of a first flip flop element of said delay circuit during a first clock pulse of said clock pulse signal, applying a second high signal to the input of a second flip flop element of said delay circuit during a second clock pulse of said clock pulse signal and applying a third high signal to the input of a third flip flop element of said delay circuit, thereby causing said clock pulse signal to be output from said delay circuit to the microprocessor based system.

Claim 18

A circuit for delaying a clock pulse signal from being output to a microprocessor based system, comprising: clock input means for providing one of a plurality of clock pulse signals having different frequencies to an input terminal; means, coupled to said clock input means, for selecting one of said plurality of clock pulse signals on the basis of predetermined information concerning the length of the delay of the output of the clock pulse signal to the microprocessor based system; and output means, coupled to said clock input, means for outputting said selected one of said plurality of clock pulse signals to said microprocessor based system.

Claim 19

The circuit according to Claim 18, wherein said clock input means comprises a multiplexer.

Claim 20

The circuit according to Claim 18, wherein said means for selecting one of said plurality of clock pulse signals comprises at least one external signal which is input to said clock input means.

Claim 21

The circuit according to Claim 18, wherein said output means comprises at least one flip flop element.

Claim 23

The method according to Claim 22, wherein said step of selecting one of said plurality of clock pulse signals comprises the step of: inputting an external signal to a multiplexer.

Claim 24

The method according to Claim 22, wherein said step of outputting said selected one of said plurality of clock pulse signals comprises the step of: outputting said selected clock pulse signal from a flip flop element to said microprocessor based system.