Reducing power consumption in a digital processor

Claim 2

1 In an information processing apparatus using a multi-tasking operating system, a method for controlling a processor clock signal wherein the supply of a processor clock signal to a processor is controlled by a program which runs in the lowest priority under said multi-tasking operating system.

Claim 3

2 The method for controlling a processor clock signal according to claim 1 wherein said program is adapted to open or to close the supply of clock signals to the processor.

Claim 4

3 The method for controlling a processor clock signal according to claim 1 wherein said program is adapted to change the frequency of the clock signal provided to the processor from an operating frequency to a reduced idle frequency and vice versa.

Claim 5

4 An information processing system including a full static processor, a clock signal generator for supplying the clock signal to said processor, and a clock signal controller for controlling the supply of the clock signal to said processor from said clock signal generator when a program given the lowest priority runs under a multi-tasking operating system.

Claim 6

4 An information processing system including a full static processor, a clock signal generator for supplying the clock signal to said processor, and a clock signal controller for controlling the supply of the clock signal to said processor from said clock signal generator when a program given the lowest priority runs under a multi-tasking operating system.

Claim 7

5 A system as claimed in claim 4 in which said clock signal controller is adapted to change the frequency of said clock signal from an operating frequency to an idling frequency and vice versa.

Claim 8

6 A system as claimed in claim 4 in which said clock signal controller is adapted to open or to close the supply of clock signals to said processor.

Claim 9

7 The information processing system according to claim 6 wherein said clock signal controller is adapted to reopen the supply of a clock signal to said processor in response to an interrupt signal to said processor.

Claim 10

8 The information processing system according to claim 7 wherein said interrupt signal is an output signal from a system timer for synchronising the entire information processing system.

Claim 11

9 An information processing system as claimed in any of claims 4 to 8 including a memory, a processor, an input/output device, a generator for supplying a clock signal to said processor, and a system timer for synchronising among the parts of the system, wherein a clock signal controller is provided for the purpose of stopping the supply of the clock signal to the processor by means of a program that runs in the lowest priority under a multi-tasking operating system and reopening the supply of said clock signal in response to an interrupt signal from said input/output device or said system timer.