US6868504B1
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US
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Interleaved delay line for phase locked and delay locked loops
Assignee: Round Rock Research LLC
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Filing: 2000-08-31
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Granted: 2005-03-15
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Expires: 2020-08-31
Abstract
Abstract An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.
Inventors
- 👤 Feng Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:11
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G11; G11C; G11C7/00; G11C7/10; G11C7/1072; G11C7/22; G11C7/222; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/0818; H03L7/085; H03L7/087; H03L7/099; H03L7/0995; H03L7/0998
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
114 words
A combination, comprising: a first locked loop for establishing a first phase relationship between an output signal and a reference signal; and a second locked loop responsive to said first locked loop and configured to establish a second phase relationship between said output signal and said reference signal, wherein said second locked loop comprises an interleaved delay line generating said output signal at an output thereof and including: a first portion providing a variable amount of load adjustment substantially independently of process, temperature and voltage variations, and a second portion in series with said first portion and providing a variable amount of drive adjustment that substantially tracks changes in process, temperature, and voltage variations.
Claim 2
Dependent Claim
114 words
A combination, comprising: a first locked loop for establishing a first phase relationship between an output signal and a reference signal; and a second locked loop responsive to said first locked loop and configured to establish a second phase relationship between said output signal and said reference signal, wherein said second locked loop comprises an interleaved delay line generating said output signal at an output thereof and including: a first portion providing a variable amount of load adjustment substantially independently of process, temperature and voltage variations, and a second portion in series with said first portion and providing a variable amount of drive adjustment that substantially tracks changes in process, temperature, and voltage variations.
Claim 3
Dependent Claim
27 words
The combination of claim 1 wherein said first portion has a small intrinsic delay and said second portion has a higher intrinsic delay than said first portion.
Claim 4
Dependent Claim
47 words
The combination of claim 1 wherein said first portion includes a delay line having a delay wherein said delay is varied by varying the load and wherein said second portion includes a variable amount of drive wherein said drive is varied by selecting a desired signal path.
Claim 5
Dependent Claim
31 words
The combination of claim 1 additionally comprising a control circuit for controlling the amount of load adjustment of said first portion and the amount of drive adjustment of said second portion.
Claim 6
Dependent Claim
70 words
An interleaved delay line, comprising: a first circuit path having a stepwise variable capacitive load; a second circuit path in series with said first circuit path and having a plurality of stages each having a fast path and a slow path; and a control circuit for controlling the amount of capacitance in said first circuit path and the number of fast paths and slow paths in said second circuit path.
Claim 7
Dependent Claim
70 words
An interleaved delay line, comprising: a first circuit path having a stepwise variable capacitive load; a second circuit path in series with said first circuit path and having a plurality of stages each having a fast path and a slow path; and a control circuit for controlling the amount of capacitance in said first circuit path and the number of fast paths and slow paths in said second circuit path.
Claim 8
Dependent Claim
26 words
The interleaved delay line of claim 5 wherein said fist circuit path has an intrinsic delay smaller than the intrinsic delay of said second circuit path.
Claim 9
Dependent Claim
34 words
The interleaved delay line of claim 5 wherein said first circuit path is substantially independent of process, temperature and voltage variations while said second circuit path substantially tracks changes in process, temperature and voltage.
Claim 10
Dependent Claim
75 words
An interleaved delay line, comprising: a first circuit path having a stepwise variable capacitive load; a second circuit path in series with said first circuit path and having a plurality of stages each having a variable amount of drive associated therewith; and a control circuit for controlling the amount of capacitance in said first circuit path and the number of stages and the amount of drive associated with each stage in said second circuit path.
Claim 11
Dependent Claim
75 words
An interleaved delay line, comprising: a first circuit path having a stepwise variable capacitive load; a second circuit path in series with said first circuit path and having a plurality of stages each having a variable amount of drive associated therewith; and a control circuit for controlling the amount of capacitance in said first circuit path and the number of stages and the amount of drive associated with each stage in said second circuit path.
Claim 12
Dependent Claim
26 words
The interleaved delay line of claim 8 wherein said first circuit path has an intrinsic delay smaller than the intrinsic delay of said second circuit path.
Claim 13
Dependent Claim
34 words
The interleaved delay line of claim 8 wherein said first circuit path is substantially independent of process, temperature and voltage variations while said second circuit path substantially tracks changes in process, temperature and voltage.
Claim 14
Dependent Claim
78 words
An interleaved delay line, comprising: a first circuit path having a plurality of stages each having a variable amount of drive associated therewith; a second circuit path in series with said first circuit path and having plurality of stages each having at least a fast and a slow path; and a control circuit for controlling the number of stages in said first circuit path and the number of fast paths and slow paths in said second circuit path.
Claim 15
Dependent Claim
78 words
An interleaved delay line, comprising: a first circuit path having a plurality of stages each having a variable amount of drive associated therewith; a second circuit path in series with said first circuit path and having plurality of stages each having at least a fast and a slow path; and a control circuit for controlling the number of stages in said first circuit path and the number of fast paths and slow paths in said second circuit path.
Claim 16
Dependent Claim
26 words
The interleaved delay line of claim 11 wherein said first circuit path has an intrinsic delay smaller than the intrinsic delay of said second circuit path.
Claim 17
Independent Claim
137 words
A method, comprising: establishing a first phase relationship between an output signal and a reference signal using a first locked loop; establishing a second phase relationship between said output signal and said reference signal using a second locked loop that is responsive to said first locked loop and configured to generate said output signal at an output thereof; propagating a signal trough two different types of variable delay circuits in said second locked loop, a first circuit providing a variable amount of load adjustment substantially independently of process, temperature and voltage variations and a second circuit in series with said first circuit and providing a variable amount of drive adjustment that substantially tracks changes in process, temperature and voltage variations; and producing control signals for controlling the amount of delay in said first and said second circuits.
Claim 18
Independent Claim
137 words
A method, comprising: establishing a first phase relationship between an output signal and a reference signal using a first locked loop; establishing a second phase relationship between said output signal and said reference signal using a second locked loop that is responsive to said first locked loop and configured to generate said output signal at an output thereof; propagating a signal trough two different types of variable delay circuits in said second locked loop, a first circuit providing a variable amount of load adjustment substantially independently of process, temperature and voltage variations and a second circuit in series with said first circuit and providing a variable amount of drive adjustment that substantially tracks changes in process, temperature and voltage variations; and producing control signals for controlling the amount of delay in said first and said second circuits.
Claim 19
Independent Claim
69 words
A method of operating a delay line, comprising: propagating a signal through a first circuit path having a stepwise variable capacitive load; propagating said signal through a second circuit path having a plurality of stages each having a fast path and a slow path; and controlling the amount of capacitance in said first circuit path and the number of fast paths and slow paths in said second circuit path.
Claim 20
Independent Claim
69 words
A method of operating a delay line, comprising: propagating a signal through a first circuit path having a stepwise variable capacitive load; propagating said signal through a second circuit path having a plurality of stages each having a fast path and a slow path; and controlling the amount of capacitance in said first circuit path and the number of fast paths and slow paths in said second circuit path.
Claim 21
Independent Claim
74 words
A method of operating a delay line, comprising: propagating a signal through a first circuit path having a step-wise variable capacitive load; propagating said signal through a second circuit path having a plurality of stages each having a variable amount of drive associated therewith; and controlling the amount of capacitance in said first circuit path and the number of stages and the amount of drive associated with each stage in said second circuit path.
Claim 22
Independent Claim
74 words
A method of operating a delay line, comprising: propagating a signal through a first circuit path having a step-wise variable capacitive load; propagating said signal through a second circuit path having a plurality of stages each having a variable amount of drive associated therewith; and controlling the amount of capacitance in said first circuit path and the number of stages and the amount of drive associated with each stage in said second circuit path.
Claim 23
Independent Claim
78 words
A method of operating a delay line, comprising: propagating a signal through a first circuit path having a plurality of stages each having a variable amount of drive associated therewith; propagating said signal through a second circuit path having a plurality of stages each having at least a fast and a slow path; and controlling the number of stages in said first circuit path and the number of fast paths and slow paths in said second circuit path.
Claim 24
Independent Claim
78 words
A method of operating a delay line, comprising: propagating a signal through a first circuit path having a plurality of stages each having a variable amount of drive associated therewith; propagating said signal through a second circuit path having a plurality of stages each having at least a fast and a slow path; and controlling the number of stages in said first circuit path and the number of fast paths and slow paths in said second circuit path.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-03-14 | 2008-09-13 | 2009-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-03-14 | 2012-09-13 | 2013-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-03-14 | 2016-09-13 | 2017-03-15 | $7700.00 | Window Closed / Lapsed |