Method and apparatus for reducing the lock time of a DLL

Claim 2

A memory device, comprising: a plurality of memory arrays addressed by row and column address decoders; a memory controller operable to control read and write operations of the memory arrays; synchronization circuitry operatively connected to the plurality of memory arrays to synchronize incoming clock signals, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit on a rising edge of a clock signal; an input clock buffer to receive an input clock signal; a normally open signal gate connected to an output of the input clock buffer to detect a rising edge of a first clock signal and a second clock signal and to pass the first and the second rising edges to the delay line; a phase detector connected to an output of the delay line to detect the rising edge of the first clock signal; and shift bit logic connected between the phase detector and the shift bit register to prevent toggling of shift bits upon detection of the edge of the first clock signal at the output of the delay line.

Claim 3

The memory device of claim 1 , and further comprising: shift logic for setting, the delay elements according to the shift bit status.

Claim 4

The memory device of claim 1 , and further comprising: dummy circuitry interposed between the end of the delay line and the phase detector.

Claim 5

A memory device, comprising: a plurality of memory arrays addressed by row and column address decoders; a memory controller operable to control read and write operations of the memory arrays; synchronization circuitry operatively connected to the plurality of memory arrays to synchronize the incoming clock signal, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit on detection of a rising edge of a clock signal; and delay line circuitry to pass two consecutive rising clock signal edges to the delay line; and edge detection circuitry at an output of the delay line to halt toggling of the shift bits upon detection of the first edge at the output of the delay line.

Claim 6

A memory device, comprising: a plurality of memory arrays addressed by row and column address decoders; a memory controller operable to control read and write operations of the memory arrays; synchronization circuitry operatively connected to the plurality of memory arrays to synchronize the incoming clock signal, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit on detection of a rising edge of a clock signal; and delay line circuitry to pass two consecutive rising clock signal edges to the delay line; and edge detection circuitry at an output of the delay line to halt toggling of the shift bits upon detection of the first edge at the output of the delay line.

Claim 7

The memory device of claim 4 , and further comprising: register address circuitry to determine a location in the shift register of a transition between shift bits having a binary one value and shift bits having a binary zero value.

Claim 8

The memory device of claim 5 , and further comprising: clock synchronization circuitry to begin clock synchronization at the determined transition.

Claim 9

The memory device of claim 4 , and further comprising: dummy circuitry interposed between the output of the delay line and the edge detection circuitry.

Claim 10

The memory device of claim 4 , wherein the edge detection circuitry is a phase detector.

Claim 11

A memory device, comprising: a plurality of memory arrays addressed by row and column address decoders; a memory controller operable to control read and write operations of the memory arrays; synchronization circuitry operatively connected to the plurality of memory arrays to synchronize the incoming clock signal, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: an adjustable delay chain having a plurality of delays and a plurality of shift bits, each shift bit corresponding to one of the plurality of delays, each shift bit operable in a first state and a second state, wherein the states are toggled by a clock signal edge passing through its respective delay; an edge detection circuit connected to an input of the delay line to pass two clock edges to the delay line; a phase detector connected to an output of the delay line to detect when the first clock signal reaches the output of the delay line; and shift bit logic connected between the phase detector and the shift bits to halt the toggling of shift bits when the first clock signal reaches the output of the delay line.

Claim 12

A memory device, comprising: a plurality of memory arrays addressed by row and column address decoders; a memory controller operable to control read and write operations of the memory arrays; synchronization circuitry operatively connected to the plurality of memory arrays to synchronize the incoming clock signal, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: an adjustable delay chain having a plurality of delays and a plurality of shift bits, each shift bit corresponding to one of the plurality of delays, each shift bit operable in a first state and a second state, wherein the states are toggled by a clock signal edge passing through its respective delay; an edge detection circuit connected to an input of the delay line to pass two clock edges to the delay line; a phase detector connected to an output of the delay line to detect when the first clock signal reaches the output of the delay line; and shift bit logic connected between the phase detector and the shift bits to halt the toggling of shift bits when the first clock signal reaches the output of the delay line.

Claim 13

A synchronous memory device, comprising: an array of memory cells addressable by a controller to control read and write operations to the memory cells; and synchronization circuitry operatively connected to the array of memory cells to synchronize incoming clock signals therebetween, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit on detection of a rising edge of a clock signal; delay line circuitry to pass two consecutive rising clock signal edges to the delay line; and edge detection circuitry at an output of the delay line to halt toggling of the shift bits upon detection of the first edge at the output of the delay line.

Claim 14

A synchronous memory device, comprising: an array of memory cells addressable by a controller to control read and write operations to the memory cells; and synchronization circuitry operatively connected to the array of memory cells to synchronize incoming clock signals therebetween, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit on detection of a rising edge of a clock signal; delay line circuitry to pass two consecutive rising clock signal edges to the delay line; and edge detection circuitry at an output of the delay line to halt toggling of the shift bits upon detection of the first edge at the output of the delay line.

Claim 15

The memory device of claim 10 , and further comprising: register address circuitry to determine a location in the shift register of a transition between shift bits having a binary one value and shift bits having a binary zero value.

Claim 16

The memory device of claim 10 , and further comprising: clock synchronization circuitry to begin clock synchronization at the determined transition.

Claim 17

The memory device of claim 10 , and further comprising: dummy circuitry interposed between the output of the delay line and the edge detection circuitry.

Claim 18

The memory device of claim 10 , wherein the edge detection circuitry is a phase detector.

Claim 19

A synchronous memory device, comprising: an array of memory cells addressable by a controller to control read and write operations to the memory cells; and synchronization circuitry operatively connected to the array of memory cells to synchronize incoming clock signals therebetween, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit as a rising edge of a clock signal passes therethrough; an input clock buffer to receive an input clock signal; a normally open signal gate connected to an output of the input clock buffer to detect an edge of a first clock signal and an edge of a second clock signal and to pass the first and the second clock signals to the delay line; a phase detector connected to an output of the delay line to detect the edge of the first clock signal; and shift bit logic connected between the phase detector and the shift bit register to prevent toggling of shift bits upon detection of the edge of the first clock signal at the output of the delay line.

Claim 20

A synchronous memory device, comprising: an array of memory cells addressable by a controller to control read and write operations to the memory cells; and synchronization circuitry operatively connected to the array of memory cells to synchronize incoming clock signals therebetween, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit as a rising edge of a clock signal passes therethrough; an input clock buffer to receive an input clock signal; a normally open signal gate connected to an output of the input clock buffer to detect an edge of a first clock signal and an edge of a second clock signal and to pass the first and the second clock signals to the delay line; a phase detector connected to an output of the delay line to detect the edge of the first clock signal; and shift bit logic connected between the phase detector and the shift bit register to prevent toggling of shift bits upon detection of the edge of the first clock signal at the output of the delay line.

Claim 21

The memory device of claim 15 , and further comprising: shift logic for setting the delay elements according to the shift bit status.

Claim 22

The memory device of claim 15 , and further comprising: dummy circuitry interposed between the end of the delay line and the phase detector.

Claim 23

An SDRAM, comprising: a plurality of memory arrays addressed by row and column address decoders; a memory controller operable to control read and write operations of the memory arrays; synchronization circuitry operatively connected to the plurality of memory arrays to synchronize incoming clock signals, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit on a rising edge of a clock signal; an input clock buffer to receive an input clock signal; a normally open signal gate connected to an output of the input clock buffer to detect a rising edge of a first clock signal and a rising edge of a second clock signal and to pass the first and the second rising edges to the delay line; a phase detector connected to an output of the delay line to detect the rising edge of the first clock signal; and shift bit logic connected between the phase detector and the shift bit register to prevent toggling of shift bits upon detection of the edge of the first clock signal at the output of the delay line.

Claim 24

An SDRAM, comprising: a plurality of memory arrays addressed by row and column address decoders; a memory controller operable to control read and write operations of the memory arrays; synchronization circuitry operatively connected to the plurality of memory arrays to synchronize incoming clock signals, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit on a rising edge of a clock signal; an input clock buffer to receive an input clock signal; a normally open signal gate connected to an output of the input clock buffer to detect a rising edge of a first clock signal and a rising edge of a second clock signal and to pass the first and the second rising edges to the delay line; a phase detector connected to an output of the delay line to detect the rising edge of the first clock signal; and shift bit logic connected between the phase detector and the shift bit register to prevent toggling of shift bits upon detection of the edge of the first clock signal at the output of the delay line.

Claim 25

The SDRAM of claim 18 , and further comprising: shift logic for setting the delay elements according to shift bit status.

Claim 26

The SDRAM of claim 18 , and further comprising: dummy circuitry interposed between the output of the delay line and the phase detector.

Claim 27

An SDRAM, comprising: a plurality of memory arrays addressed by row and column address decoders; a memory controller operable to control read and write operations of the memory arrays; synchronization circuitry operatively connected to the plurality of memory arrays to synchronize the incoming clock signal, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit in response to a rising edge of a clock signal; delay line circuitry to pass two consecutive rising clock signal edges to the delay line; and edge detection circuitry at an output end of the delay line to halt toggling of the shift bits upon detection of the first edge at the output end of the delay line.

Claim 28

An SDRAM, comprising: a plurality of memory arrays addressed by row and column address decoders; a memory controller operable to control read and write operations of the memory arrays; synchronization circuitry operatively connected to the plurality of memory arrays to synchronize the incoming clock signal, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: a delay line having a plurality of delay elements and a plurality of shift bits in a shift bit register, each shift bit operatively connected to one of the plurality of delay elements to toggle each shift bit in response to a rising edge of a clock signal; delay line circuitry to pass two consecutive rising clock signal edges to the delay line; and edge detection circuitry at an output end of the delay line to halt toggling of the shift bits upon detection of the first edge at the output end of the delay line.

Claim 29

The SDRAM of claim 21 , and further comprising: register address circuitry to determine a location in the shift register of a transition between shift bits having a binary one value and shift bits having a binary zero value.

Claim 30

The SDRAM of claim 22 , and further comprising: clock synchronization circuitry to begin clock synchronization at the determined transition.

Claim 31

The SDRAM of claim 21 , and further comprising: dummy circuitry interposed between the output end of the delay line and the edge detection circuitry.

Claim 32

The SDRAM of claim 21 , wherein the edge detection circuitry is a phase detector.

Claim 33

An SDRAM, comprising: a plurality of memory arrays addressed by row and column address decoders; a memory controller operable to control read and write operations of the memory arrays; synchronization circuitry operatively connected to the plurality of memory arrays to synchronize the incoming clock signal, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: an adjustable delay chain having a plurality of delays and a plurality of shift bits, each shift bit corresponding to one of the plurality of delays, each shift bit operable in a first state and a second state, wherein the states are toggled by a clock signal edge passing through its respective delay; an edge detection circuit connected to an input of the delay line to pass two clock edges to the delay line; a phase detector connected to an output of the delay line to detect when the first clock signal reaches the output of the delay line; and shift bit logic connected between the phase detector and the shift bits to halt the toggling of shift bits when the first clock signal reaches the output of the delay line.

Claim 34

An SDRAM, comprising: a plurality of memory arrays addressed by row and column address decoders; a memory controller operable to control read and write operations of the memory arrays; synchronization circuitry operatively connected to the plurality of memory arrays to synchronize the incoming clock signal, wherein the synchronization circuitry comprises a delay locked loop, the delay locked loop comprising: an adjustable delay chain having a plurality of delays and a plurality of shift bits, each shift bit corresponding to one of the plurality of delays, each shift bit operable in a first state and a second state, wherein the states are toggled by a clock signal edge passing through its respective delay; an edge detection circuit connected to an input of the delay line to pass two clock edges to the delay line; a phase detector connected to an output of the delay line to detect when the first clock signal reaches the output of the delay line; and shift bit logic connected between the phase detector and the shift bits to halt the toggling of shift bits when the first clock signal reaches the output of the delay line.