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US6787908B2
Expired / Lapsed
US
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Pad metallization over active circuitry
Assignee: Philips Semiconductors Inc
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Filing: 2001-06-05
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Granted: 2004-09-07
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Expires: 2021-06-05
Abstract
Abstract Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.
Inventors
- 👤 Steven L Skala
- 👤 Subhas Bothra
- 👤 Emmanuel Demuizon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:12
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W72/01; H10W72/012; H10W72/20; H10W72/251; H10W72/29; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/59; H10W72/931; H10W72/934; H10W72/951; H10W72/952
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
133 words
A semiconductor chip having circuitry, the semiconductor chip comprising: a metal bond pad over the circuitry and insulated on at least two sides by passivation material; a diffusion barrier layer over the metal bond pad, at least two entire sides of the diffusion barrier layer being insulated by the passivation material, wherein the diffusion barrier layer includes TiN; and a metal layer over the circuitry, the metal bond pad, the diffusion barrier layer, and at least partially over, and in contact with, a portion of the passivation material not over the diffusion barrier layer, the metal layer being configured and arranged for connecting to a wire bond, wherein the diffusion barrier layer is constructed and arranged to mitigate inter-metallic compounds forming as a reaction to the metal layer connecting to the wire bond.
Claim 2
Dependent Claim
133 words
A semiconductor chip having circuitry, the semiconductor chip comprising: a metal bond pad over the circuitry and insulated on at least two sides by passivation material; a diffusion barrier layer over the metal bond pad, at least two entire sides of the diffusion barrier layer being insulated by the passivation material, wherein the diffusion barrier layer includes TiN; and a metal layer over the circuitry, the metal bond pad, the diffusion barrier layer, and at least partially over, and in contact with, a portion of the passivation material not over the diffusion barrier layer, the metal layer being configured and arranged for connecting to a wire bond, wherein the diffusion barrier layer is constructed and arranged to mitigate inter-metallic compounds forming as a reaction to the metal layer connecting to the wire bond.
Claim 3
Dependent Claim
21 words
The semiconductor chip of claim 1 , wherein the diffusion barrier layer has a thickness that is at least 0.5 micron.
Claim 4
Dependent Claim
21 words
The semiconductor chip of claim 1 , wherein the diffusion barrier layer has a thickness that is at least 1.0 micron.
Claim 5
Dependent Claim
19 words
The semiconductor chip of claim 1 , wherein the semiconductor chip is configured and arranged as a flip chip.
Claim 6
Dependent Claim
14 words
The semiconductor chip of claim 1 , wherein the metal bond pad includes aluminum.
Claim 7
Dependent Claim
14 words
The semiconductor chip of claim 5 , wherein the diffusion barrier layer includes TiN.
Claim 8
Dependent Claim
35 words
The semiconductor chip of claim 6 , wherein the diffusion barrier layer is further constructed and arranged to mitigate inter-metallic AI/Au compounds forming as a reaction to the metal layer connecting to the wire bond.
Claim 9
Dependent Claim
34 words
The semiconductor chip of claim 7 , wherein the diffusion barrier layer has a thickness that is at least 0.5 micron, and the metal layer has a thickness that is at least 3 microns.
Claim 10
Dependent Claim
22 words
The semiconductor chip of claim 1 , wherein the metal bond pad and the metal layer include the same type of metal.
Claim 11
Dependent Claim
128 words
A semiconductor chip having circuitry, the semiconductor chip comprising: an aluminum bond pad over the circuitry and insulated on at least two sides by passivation material; a diffusion barrier layer, including TiN, over the aluminum bond pad, at least two entire sides of the diffusion layer being insulated by the passivation material; and a metal layer over the circuitry, the metal bond pad, the diffusion barrier layer, and at least partially over, and in contact with, a portion of the passivation material not over the diffusion barrier layer, the metal layer being configured and arranged for connecting to a wire bond and the diffusion barrier layer being constructed and arranged to mitigate inter-metallic aluminum-based compounds forming as a reaction to the metal layer connecting to the wire bond.
Claim 12
Dependent Claim
128 words
A semiconductor chip having circuitry, the semiconductor chip comprising: an aluminum bond pad over the circuitry and insulated on at least two sides by passivation material; a diffusion barrier layer, including TiN, over the aluminum bond pad, at least two entire sides of the diffusion layer being insulated by the passivation material; and a metal layer over the circuitry, the metal bond pad, the diffusion barrier layer, and at least partially over, and in contact with, a portion of the passivation material not over the diffusion barrier layer, the metal layer being configured and arranged for connecting to a wire bond and the diffusion barrier layer being constructed and arranged to mitigate inter-metallic aluminum-based compounds forming as a reaction to the metal layer connecting to the wire bond.
Claim 13
Dependent Claim
33 words
The semiconductor chip of claim 10 , wherein the diffusion barrier layer has a thickness that is at least 0.5 micron, the metal layer has a thickness that is at least 3 microns.
Claim 14
Dependent Claim
35 words
The semiconductor chip of claim 11 , wherein the diffusion barrier layer is further constructed and arranged to mitigate inter-metallic Al/Au compounds forming as a reaction to the metal layer connecting to the wire bond.
Claim 15
Dependent Claim
131 words
A semiconductor chip having circuitry, the semiconductor chip comprising: an aluminum bond pad over the circuitry and insulated on at least two sides by means for electrically insulating the aluminum bond pad; barrier means, including TiN, over the aluminum bond pad, at least two entire sides of the diffusion layer being insulated by the passivation material; and a metal layer over the circuitry, the metal bond pad, the barrier means, and at least partially over, and in contact with, a portion of the means for electrically insulating the aluminum bond pad not over the barrier means, the metal layer being configured and arranged for connecting to a wire bond and the barrier means for mitigating inter-metallic aluminum-based compounds forming as a reaction to the metal layer connecting to the wire bond.
Claim 16
Dependent Claim
131 words
A semiconductor chip having circuitry, the semiconductor chip comprising: an aluminum bond pad over the circuitry and insulated on at least two sides by means for electrically insulating the aluminum bond pad; barrier means, including TiN, over the aluminum bond pad, at least two entire sides of the diffusion layer being insulated by the passivation material; and a metal layer over the circuitry, the metal bond pad, the barrier means, and at least partially over, and in contact with, a portion of the means for electrically insulating the aluminum bond pad not over the barrier means, the metal layer being configured and arranged for connecting to a wire bond and the barrier means for mitigating inter-metallic aluminum-based compounds forming as a reaction to the metal layer connecting to the wire bond.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-09-07 | 2008-03-08 | 2008-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-09-07 | 2012-03-08 | 2012-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-09-07 | 2016-03-08 | 2016-09-07 | $7700.00 | Window Closed / Lapsed |