Semiconductor chips suitable for known good die testing

Claim 1

A method of making a semiconductor device having enhanced performance in KNOWN GOOD DIE test protocols comprising providing a semiconductor chip or die comprising a substrate with a surface containing integrated circuits interconnected with at least one bond pad, the die having a primary passivation layer that overlays the circuits and overlaps edges of the bond pad terminating in a tapered window forming an opening over the bond pad, A. applying a resin-containing flowable liquid composition as part of the primary passivation layer, or on top of the primary passivation layer to planarize the surface; B. heating the composition to a temperature sufficient to stabilize it; C. applying an amorphous silicon carbide coating to the layer formed in step A to provide chemical and mechanical protection to the die; D. exposing a portion of the bond pad by fabricating an opening through the layers applied in steps A--C; E. optionally depositing and patterning a first diffusion barrier metal layer on the exposed portion of the bond pad, the first metal layer overlapping the opening in the primary passivation layer; and F. depositing a second conductive metal layer on the first metal layer above the bond pad, or if no first metal layer is deposited, then depositing the second metal layer on the exposed portion of the bond pad.

Claim 2

A method of making a semiconductor device having enhanced performance in KNOWN GOOD DIE test protocols comprising providing a semiconductor chip or die comprising a substrate with a surface containing integrated circuits interconnected with at least one bond pad, the die having a primary passivation layer that overlays the circuits and overlaps edges of the bond pad terminating in a tapered window forming an opening over the bond pad, A. applying a resin-containing flowable liquid composition as part of the primary passivation layer, or on top of the primary passivation layer to planarize the surface; B. heating the composition to a temperature sufficient to stabilize it; C. applying an amorphous silicon carbide coating to the layer formed in step A to provide chemical and mechanical protection to the die; D. exposing a portion of the bond pad by fabricating an opening through the layers applied in steps A--C; E. optionally depositing and patterning a first diffusion barrier metal layer on the exposed portion of the bond pad, the first metal layer overlapping the opening in the primary passivation layer; and F. depositing a second conductive metal layer on the first metal layer above the bond pad, or if no first metal layer is deposited, then depositing the second metal layer on the exposed portion of the bond pad.